Memory implementations of shift registers

Details Memory implementations of shift registers Memory implementations of shift registers

2006-08-15

2006-08-15

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S170000, C711S167000, C711S155000, C711S104000, C711S109000

Reexamination Certificate

active

07093084

ABSTRACT:
A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the result of reading data from each column and presenting it for writing in the next column. To compensate for latency (delay) in the column-to-column data transfer, the circuitry that controls reading is kept ahead of the circuitry that controls writing by a number of read/write cycles that takes approximately the same amount of time as the column-to-column data transfer delay.

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