Memory hole modification and mixed technique arrangements...

Details Memory hole modification and mixed technique arrangements... Memory hole modification and mixed technique arrangements...

2001-03-30

2004-02-17

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S118000, C711S138000, C711S170000

Reexamination Certificate

active

06694418

ABSTRACT:

FIELD
The present invention is directed to efficient defining of cacheable memory space. More particularly, the present invention is directed to memory hole modification and mixed technique arrangements for maximizing cacheable memory space.
BACKGROUND
The computer industry's devotion, commitment and adherence to support long existing BIOS (basic input/output system) functions have advantageously helped fuel the wide-spread (i.e., global) acceptance of computers and the explosion of the computer industries. However, such commitment and adherence have likewise been found to result in disadvantages as follows.
More particularly, BIOS has historically been embodied as an assembly language (i.e., machine code) program which is first loaded (even before the operating system (OS)) when a computer is started, and which provides the most basic, low-level, intimate control and supervision operations for the computer. More specifically, BIOS performs functions such as: POST (power-on/self-test); acting as an intermediary between different hardware; setting up (i.e., defining) cacheable memory space, finding/loading the OS (operating system), etc.
With regard to setting up (i.e., initializing) of a system, typically within processor systems, a portion of memory will be set aside (i.e., reserved) for use as cacheable memory space to serve as a fast internal cache memory for the purposes of “caching” slower physical memory in the system in an overall effort to increase the system's performance. The size of the portion of memory set aside for cacheable memory space may vary greatly from system to system, e.g., the cacheable memory space may be 64 MB (i.e., mega-byte), 106 MB, 3.5 GB (i.e., giga-byte), etc. It is extremely advantageous that a size of defined cacheable memory space be maximized, as such will typically lead to increased (i.e., faster) system performance.
Historically, BIOS programming has been embodied in a singular or small number of monolithic blocks of intertwined assembly or machine code, such monolithic nature being illustrated by the singular dashed block
11
drawn around all of
FIG. 1
BIOS functions. Intertwining often meant that changes were very difficult to make, as changes in one portion of the code often affected the operation of remaining portions of the code. Accordingly, BIOS code is disadvantageously very difficult to write, debug and/or change. In view of BIOS' difficult assembly language programming and debugging, hardware companies typically have relied upon BIOS specialist companies (e.g., American Megatrends Inc. (AMI), Award Software, Microid Research (MR), Phoenix Technologies Ltd.) to provide BIOS code.
The desire for adherence to long existing BIOS code and the complexity of BIOS have sometimes resulted in complacency in the industry, resulting in minimal or no advances in some of the BIOS functions. The BIOS function of setting up (i.e., defining) of cacheable memory space is one function in need of improvement.


REFERENCES:
patent: 5946713 (1999-08-01), Hacking et al.
patent: 6134641 (2000-10-01), Anand
patent: 6363473 (2002-03-01), Volentine et al.
patent: 6408384 (2002-06-01), Adams

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