Memory hierarchy reconfiguration for energy and performance...

Details Memory hierarchy reconfiguration for energy and performance... Memory hierarchy reconfiguration for energy and performance...

2006-12-21

2010-11-23

Phung, Anh (Department: 2824)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C365S049130

Reissue Patent

active

RE041958

ABSTRACT:
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

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Stolowitz Ford Cowger LLP; Related Case Listing Sheet; Apr. 9, 2010; 1 Page.
Balasubramonian et al.; Dynamic Memory Hierarchy Performance Optimization; International Symposium on Computer Architecture; Jul. 11, 2000.

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