Memory having storage means

Details Memory having storage means Memory having storage means

2003-03-19

2004-09-21

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S145000, C365S189080

Reexamination Certificate

active

06795351

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory.
2. Description of the Background Art
In general, volatile and nonvolatile memories are known as semiconductor memories. A DRAM (dynamic random access memory) is known as the nonvolatile memory, and a flash EEPROM (electrically erasable and programmable read only memory) is known as the nonvolatile memory. The DRAM and the flash EEPROM, which can be highly integrated, are widely employed.
FIG. 58
is an equivalent circuit diagram showing the structure of a memory cell
103
of a conventional DRAM.
FIG. 59
is a sectional view showing the structure of a trench-type capacitor
102
employed for the conventional DRAM. Referring to
FIG. 58
, the memory cell
103
of the conventional DRAM serving as a nonvolatile memory is formed by a selection transistor
101
and the capacitor
102
. The capacitor
102
stores information of the memory cell
103
as charges. In order to read information from the memory cell
103
, a word line WL rises to bring the selection transistor
101
into an ON state. Thus, a cell capacitance Ccell and a bit line capacitance Cb1 are capacitively coupled with each other. Therefore, a bit line potential depending on the quantity of the charges stored in the memory cell
103
can be read.
In the memory cell
103
of the conventional DRAM having the aforementioned structure, an upper electrode
102
a
, a lower electrode
102
c
and a dielectric film
102
b
forming the trench-type capacitor
102
are longitudinally extended as shown in
FIG. 59
, in order to ensure the cell capacitance Ccell of the capacitor
102
also when the same is refined. If refinement further progresses, however, it is difficult to ensure the capacitance of the capacitor
102
also when employing the trench structure shown in FIG.
59
. In other words, high integration of the DRAM resulting from reduction of a design rule approaches to the limit.
In the flash EEPROM (hereinafter referred to as a flash memory) serving as the nonvolatile memory, a memory cell of a CHE (channel hot electron) system such as a stacked or split gate memory cell is limited in refinement of the channel length. In a memory cell of an FN (Fouler-Nordheim) write system such as a NAND memory cell, the limit of refinement is equivalent to that of a logic transistor. However, the flash memory requires a high voltage of 15 V to 20 V for operations, and if the power supply voltage for the logic transistor is reduced, efficiency for forming the high voltage of 15 V to 20 V from the low power supply voltage is reduced. Therefore, power consumption is increased and the area of a charge pumping part is also increased, to disadvantageously hinder refinement.
A ferroelectric memory is known as one of recently noted nonvolatile memories. The ferroelectric memory utilizes pseudo capacitance change resulting from the direction of polarization of a ferroelectric substance as a memory element. The ferroelectric memory, capable of rewriting data at a high speed with a low voltage in principle, is spotlighted as an ideal memory having the advantages of the high speed and the low voltage of the DRAM as well as the advantage of nonvolatility of the flash memory.
Memory cell systems for a ferroelectric memory are roughly classified into three types of systems, i.e., a one-transistor one-capacitor system, a simple matrix system and a one-transistor system.
FIG. 60
is an equivalent circuit diagram showing a memory cell
113
of a one-transistor one-capacitor ferroelectric memory.
FIG. 61
is an equivalent circuit diagram showing a memory cell array of a simple matrix ferroelectric memory.
FIG. 62
is a hysteresis diagram for illustrating operations of the simple matrix ferroelectric memory, and
FIG. 63
is a hysteresis diagram for illustrating disturbance in the simple matrix ferroelectric memory.
FIG. 64
is an equivalent circuit diagram showing a memory cell
131
of a one-transistor ferroelectric memory, and
FIG. 65
is a hysteresis diagram for illustrating operations of the one-transistor ferroelectric memory.
FIG. 66
is an equivalent circuit diagram for illustrating a voltage application state in writing of the one-transistor ferroelectric memory shown in
FIG. 64
, and
FIG. 67
is an equivalent circuit diagram for illustrating a voltage application state in a standby state of the one-transistor ferroelectric memory shown in FIG.
64
.
As shown in
FIG. 60
, the memory cell
113
of the one-transistor one-capacitor ferroelectric memory is formed bya selection transistor
111
and a ferroelectric capacitor
112
, similarly to that of the DRAM. The memory cell
113
is different from that of the DRAM in the ferroelectric capacitor
112
. In operation, a word line WL rises for bringing the selection transistor
111
into an ON state. Thus, a capacitor capacitance Ccell of the ferroelectric capacitor
112
is connected with a bit line capacitance Cb1. Then, a plate line PL is pulse-driven for transmitting charges in a quantity varying with the direction of polarization of the ferroelectric capacitor
112
. The ferroelectric memory reads data as the voltage of the bit line BL, similarly to the case of the DRAM.
In the one-transistor one-capacitor ferroelectric memory having a structure similar to that of the DRAM, refinement of the ferroelectric capacitor
112
is limited. Therefore, the ferroelectric memory is limited in high integration similarly to the DRAM.
The simple matrix ferroelectric memory is now described with reference to
FIGS. 61
to
63
. As shown in
FIG. 61
, each memory cell
121
of the simple matrix ferroelectric memory is constituted by a ferroelectric capacitor
122
consisting of a word line WL and a bit line BL formed to extend in directions intersecting with each other and a ferroelectric film (not shown) arranged between the word line WL and the bit line WL. An end of the ferroelectric capacitor
122
is connected to the word line WL while another end thereof is connected to the bit line BL. The simple matrix ferroelectric memory, reading a potential resulting from capacitive coupling between the bit line BL and the ferroelectric capacitor
122
, must ensure capacitances similarly to the DRAM. In the simple matrix ferroelectric memory, however, each memory cell
121
is formed by only the ferroelectric capacitor
122
with no selection transistor, whereby the degree of integration can be improved as compared with the one-transistor one-capacitor ferroelectric memory.
Operations of the simple matrix ferroelectric memory are now described with reference to
FIGS. 61 and 62
. Table 1 shows voltages applied to each cell
121
in reading/writing.
TABLE 1
Standby
Reading
Writing “1”
Writing “0”
Selected WL
½ Vcc
Vcc
0
Vcc
Non-Selected WL
½ Vcc
⅓ Vcc
⅔ Vcc
⅓ Vcc
Selected BL
½ Vcc
0→Floating
Vcc
0
Non-Selected BL
½ Vcc
⅔ Vcc
⅓ Vcc
⅔ Vcc
In a write operation, both ends of the ferroelectric capacitor
122
are at the same potential in a standby state. In order to write data “0”, the simple matrix ferroelectric memory applies a voltage Vcc to the word line WL while applying a voltage of 0 V to the bit line BL. At this time, the simple matrix ferroelectric memory applies the voltage Vcc to the ferroelectric capacitor
122
, thereby making a transition to a point A shown in FIG.
62
. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor
122
to the same potential, for making a transition to “0” shown in FIG.
62
. In order to write data “1”, the simple matrix ferroelectric memory applies the voltage 0 V to the word line WL while applying the voltage Vcc to the bit line BL. At this time, the simple matrix ferroelectric memory applies a voltage −Vcc to the ferroelectric capacitor
122
, thereby making a transition to a point B in FIG.
62
. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor
122
to the same potential, for making a transition

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