Memory having parity error correction

Details Memory having parity error correction Memory having parity error correction

2005-06-15

2008-10-21

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189040, C365S200000, C365S202000

Reexamination Certificate

active

07440309

ABSTRACT:
A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

REFERENCES:
patent: 5289421 (1994-02-01), Lee et al.
patent: 5963489 (1999-10-01), Kirihata et al.
patent: 6838331 (2005-01-01), Klein
patent: 2003/0149929 (2003-08-01), White
patent: 2004/0117723 (2004-06-01), Foss
patent: 2004/0221098 (2004-11-01), Ito et al.
patent: 2005/0201141 (2005-09-01), Turner

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