Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2002-12-23
2004-06-22
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S230020
Reexamination Certificate
active
06754130
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly, to providing a more capable memory from less capable memory components.
2. Background Information
It is known to combine multiple memory components, such as static random access memory devices, to produce a larger memory array having enhanced capability. For example, smaller memory components can be combined in an array to form a wider memory (i.e., a memory wherein the addressable locations include a larger number of bits). Each of the smaller memory components that form the array have common address and control signals, but have separate data in and data out signals. Alternately, smaller memory components can be combined into an array to form a larger memory of increased depth (i.e., a memory with a large number of addressable locations). Such arrays involve the use of decoders and read data multiplexers. In combining smaller memory components to form a memory array, focus has been on the desired width or depth of the memory array, and the address signals used.
Some design systems allow designers to create a circuit of connected components selected from a design library. The maximum number of write ports on any memory device to be included in the circuit is limited by the memory components available in the design library. For the case of Field Programmable Gate Arrays (FPGAs), the design library includes of the primitive hardware structures of the FPGA (e.g. configurable logic blocks or block RAMs) and any higher-level design elements provided by a “core generator” or other such FPGA design tools. Similarly, for Application Specific Integrated Circuits (ASICs), the design library includes a fixed number of standard-cell or other pre-verified component designs. For these and other technologies, any design that involves a memory with more than the maximum number of write ports supported by the design library is unrealizable in that technology.
SUMMARY OF THE INVENTION
Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than one. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses, and having less than N write ports. The memory also has a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory unit having less than N write ports. The memory includes a control unit configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units, each having less than N write ports. The control unit comprises at least one write-insert unit producing insert data for one of the control memory units, the at least one write-insert unit receiving read data from at least one other control memory unit.
Exemplary embodiments of the present invention are also directed to a method for operating a memory including providing a memory having N write ports, where N is greater than 1, the memory being constructed from multiple data memory units each having less than N write ports and having a range of addressable storage locations. The method comprises supplying information to an addressable location of the memory which falls within the range of addressable locations, and updating a control memory unit having less than N write ports to indicate which of the multiple data memory units contains the information. The updating includes reading at least one value of at least one control memory unit; determining an insert value from the at least one value of at least one control memory unit; and writing the insert value into a control memory unit.
The present invention is also directed to a control unit for memory having N write ports, where N is greater than 1. The control unit includes a number of control memory units, each control memory unit having less than N write ports. The control unit also includes at least one write-insert unit producing insert data for one of the control memory units, the at least one write-insert unit receiving data read from at least one other control memory unit. The control unit includes at least one select unit receiving read data from the control memory units at a read address provided to the memory, the at least one select unit producing an indication of a data memory unit.
The present invention is further directed to a system having an memory. The system including a memory constructed of multiple data memory units and a control unit. The memory has N write ports, wherein N is greater than 1. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses, and having less than N write ports. The memory includes a second data memory unit having a plurality of storage locations addressable by the range of addresses. The second data memory unit has less than N write ports. The memory includes a control unit configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units. Each control memory unit has less than N write ports. The control unit comprises at least one write-insert unit producing insert data for one of the control memory units. The at least one write-insert unit receives read data from at least one other control memory unit. The system also includes logic configured to access the memory.
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Hewlett-Packard Development Company LP.
Lebentritt Michael S.
Nguyen Hien
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