Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2002-12-23
2003-11-25
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S189011
Reexamination Certificate
active
06654308
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly, to providing a more capable memory from less capable memory components.
2. Background Information
It is known to combine multiple memory components, such as static random access memory devices, to produce a larger memory array having enhanced capability. For example, smaller memory components can be combined in an array to form a wider memory (i.e., a memory wherein the addressable locations include a larger number of bits). Each of the smaller memory components that form the array have common address and control signals, but have separate data in and data out signals. Alternately, smaller memory components can be combined into an array to form a larger memory of increased depth (i.e., a memory with a larger number of addressable locations). Such arrays involve the use of decoders and read data multiplexers. In combining smaller memory components to form a memory array, focus has been on the desired width or depth of the memory array, and the address signals used.
Some design systems allow designers to create a circuit of connected components selected from a design library. The maximum number of write ports on any memory device to be included in the circuit is limited by the memory components available in the design library. For the case of Field Programmable Gate Arrays (FPGAs), the design library includes the primitive hardware structures of the FPGA (e.g. configurable logic blocks or block RAMs) and any higher-level design elements provided by a “core generator” or other such FPGA design tools. Similarly, for Application Specific Integrated Circuits (ASICs), the design library includes of a fixed number of standard-cell or other pre-verified component designs. For these and other technologies, any design that involves a memory with more than the maximum number of write ports supported by the design library is unrealizable in that technology.
SUMMARY OF THE INVENTION
Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than two. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses, and having less than N write ports. The memory also has a second data memory unit having a plurality of storage locations addressable by the range of addresses. The second data memory unit has less than N write ports. The memory further includes a control unit configured to select among the first and second data memory units in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units, each having less than N write ports. One of the control memory units has a first and second write port and is configured such that a first value is written through the first write port when a predetermined write port associated with the first data memory unit is used to write, and such that a second value is written through the second write port when another predetermined write port associated with the second data memory unit is used to write. The first and second values are determined independently of data read from a control memory unit.
Exemplary embodiments of the present invention are also directed to a method for operating a memory including the steps of providing a memory having N write ports, where N is greater than 2, the memory is constructed from multiple data memory units each having less than N write ports and having a range of addressable storage locations. The method comprises supplying information to an addressable location of the memory which falls within the range of addressable locations, and updating a control memory unit by writing a first value through a first write port of the control memory unit when a predetermined write port associated with a first data memory unit is used to write, and by writing a second value through a second write port of the control memory unit when another predetermined write port associated with the second data memory unit is used to write. The first and second values are determined independently of data read from a control memory unit.
The present invention is also directed to a control unit for memory having N write ports, where N is greater than 2. The control unit includes multiple control memory units, each having less than N write ports. One of the control memory units has first and second write ports and is configured such that a first value is written through the first write port when a predetermined write port associated with the first data memory unit is used to write, and such that a second value is written through the second write port when another predetermined write port associated with the second data memory unit is used to write. The control unit also includes at least one select unit receiving read data from the control memory units at a read address provided to the memory, the at least one select unit producing an indication of a data memory unit. The first and second values are determined independently of data read from a control memory unit.
The present invention is further directed to a system including a memory. The memory has N write ports, wherein N is greater than 2. The memory comprises a first data memory unit with a plurality of storage locations addressable by a range of addresses. The first data memory unit has less than N write ports. The memory has a second data memory unit having a plurality of storage locations addressable by the range of addresses. The second data memory unit has less than N write ports. The control unit is configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units, each having less than N write ports. One of the multiple control memory units has first and second write ports and is configured such that a first value is written through the first write port when a predetermined write port associated with the first data memory unit is used to write, and such that a second value is written through the second write port when another predetermined write port associated with the second data memory unit is used to write. The first and second values are determined independently of data read from a control memory unit. The system includes logic configured to access the memory.
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Phung Anh
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