Static information storage and retrieval – Read/write circuit
Patent
1992-07-06
1993-12-07
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
365203, G11C 700
Patent
active
052688631
ABSTRACT:
A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.
REFERENCES:
patent: 4581718 (1986-04-01), Oishi
patent: 4916670 (1990-04-01), Suzuki
patent: 4926387 (1990-05-01), Madland
patent: 4975877 (1990-12-01), Bell
patent: 4995002 (1991-02-01), Yamada et al.
patent: 5018111 (1991-05-01), Madland
patent: 5146427 (1992-09-01), Sasaki
patent: 5187684 (1993-02-01), Hoshino
Bader Mark D.
Chang Ray
Jones Kenneth W.
Wang Karl L.
Hill Daniel D.
LaRoche Eugene R.
Motorola Inc.
Zarabian A.
LandOfFree
Memory having a write enable controlled word line does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory having a write enable controlled word line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory having a write enable controlled word line will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2020623