Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-12-04
2002-12-03
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S195000
Reexamination Certificate
active
06490225
ABSTRACT:
FIELD OF THE DISCLOSURE
The present disclosure relates generally to dynamic random access memories (DRAM), and more particularly to DRAM controller-array configurations.
BACKGROUND
A primary consideration in designing random access memory (RAM) is the speed at which the RAM can respond to access requests. If the RAM is used in a computing system and the RAM is too slow in responding to either read or write access requests, then the overall performance of the system can be degraded. The speed of the RAM becomes even more important when used with today's faster processors.
Some types of conventional RAM, such as static random access memory (SRAM), have faster access times and provide generally superior performance to other types of RAM, but are physically large and expensive. Other types of conventional RAM, such as dynamic random access memory (DRAM), are physically smaller and less expensive than SRAM, but generally have slower access times. In attempting to gain the benefits of both SRAM and DRAM in systems requiring fast memory access, designers often use DRAM for “bulk” storage, and SRAM to cache data traveling between a processor and the DRAM. Using SRAM to cache data in this manner provides a performance improvement over the use of conventional DRAM alone, by reducing the number of DRAM accesses required, and yet still allowing the largest portion of RAM to be relatively inexpensive.
In part because of the success of the SRAM/DRAM combination in which data is normally read from sequential addresses within a DRAM and cached in an SRAM for later random access, traditional DRAM designs have focused on improving the sequential output speed of the DRAM. This improvement in sequential access speed often comes at the expense of the DRAM's random access speed. Unfortunately, this sacrifice of random access speed for improved sequential access speed is not acceptable in all situations. For example, when a DRAM is used without an SRAM cache, the DRAM will need to make many more random accesses. As a result of the increased number of random accesses required by a DRAM operating without an SRAM cache, a DRAM optimized for sequential access, will not provide optimum overall performance in this situation.
Additionally, traditional DRAM designs require the array portion of a DRAM to operate according to fixed timing parameters. For example, in extended-data-out-DRAMs (EDO) a memory controller governs the timing within the DRAM's memory array by asserting and de-asserting separate timing signals. Similarly, in synchronous DRAMs (SDRAM), a memory controller governs the internal timing of the DRAM's memory array activity based on a number of clock cycles.
Designers wishing to obtain optimum performance using fixed timing parameters such as those used in conventional EDO or SDRAM, must design the DRAM to operate at a particular frequency. Consider the case where the DRAM is designed for use in a system that is being developed to operate at 100 MHz, but in fact the system operates at only 98.9 MHz when completed. This slight change in operating frequency could be enough to reduce the access time of the DRAM by a full clock cycle, and therefore require re-engineering of the DRAM, software, or an interrelated system.
It should be apparent from the above discussion that conventional DRAM technology is less than perfect, and it would be advantageous to have a memory that overcame at least some of the limitations disclosed above.
REFERENCES:
patent: 5276858 (1994-01-01), Oak et al.
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patent: 6272588 (2001-08-01), Johnston et al.
patent: 6288959 (2001-09-01), OuYang et al.
Silicon7's 8-Mbit SRAM Sports Single-Transistor Cell, Sep. 11, 2001.
1T-SRAM Ultra-High Density SRAM 0.18 Micron Pure Logic, 1999.
Andre Tom
Millar Brian M.
Dinh Son T.
Motorola Inc.
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