Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2007-02-22
2010-06-29
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S210150, C365S230010, C365S233100, C365S205000, C365S207000, C365S208000
Reexamination Certificate
active
07746716
ABSTRACT:
A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.
REFERENCES:
patent: 5058062 (1991-10-01), Wada et al.
patent: 5329176 (1994-07-01), Miller, Jr. et al.
patent: 5357480 (1994-10-01), Vinal
patent: 5388075 (1995-02-01), Vinal
patent: 5619464 (1997-04-01), Tran
patent: 5999482 (1999-12-01), Kornachuk et al.
patent: 6061293 (2000-05-01), Miller et al.
patent: 6181626 (2001-01-01), Brown
patent: 6275070 (2001-08-01), Pantelakis et al.
patent: 6282131 (2001-08-01), Roy
patent: 6483754 (2002-11-01), Agrawal
patent: 6711092 (2004-03-01), Sabharwal
patent: 6831853 (2004-12-01), Lin et al.
patent: 6894943 (2005-05-01), Suzuki et al.
patent: 6950362 (2005-09-01), Kurumada et al.
patent: 7035149 (2006-04-01), Shimizu
patent: 7161855 (2007-01-01), Kodama
patent: 7251179 (2007-07-01), Ohsawa
patent: 7355915 (2008-04-01), Gouin et al.
patent: 7499347 (2009-03-01), Chen et al.
patent: 2002/0145932 (2002-10-01), Nguyen et al.
patent: 2002/0186579 (2002-12-01), Yokozeki
patent: 2003/0099128 (2003-05-01), Peterson et al.
patent: 2003/0202399 (2003-10-01), Nguyen et al.
patent: 2005/0020739 (2005-01-01), Dittrich et al.
patent: 2005/0104627 (2005-05-01), Song
patent: 2005/0180228 (2005-08-01), Canada et al.
patent: 2005/0207239 (2005-09-01), Kodama
patent: 10-1995-0009878 (1995-09-01), None
Chen et al., Patent Application Publication US 2008/0037338 A1 (U.S. Appl. No. 11/614,828).
Stackhouse et al., Patent Application Publication US 2004/0257882 A1 (U.S. Appl. No. 10/600,875).
International Search Report for coordinating PCT Application No. PCT/US08/51843 mailed Apr. 28, 2008.
Office Action mailed Jul. 9, 2008 on Related U.S. Appl. No. 11/536,136.
Notice of Allowance mailed Dec. 5, 2008 on Related U.S. Appl. No. 11/536,136.
Childs Lawrence F.
Jetton Mark W.
Lu Olga R.
Starnes Glenn E.
Freescale Semiconductor Inc.
Hill Susan C.
Phan Trong
Singh Ranjeev
LandOfFree
Memory having a dummy bitline for timing control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory having a dummy bitline for timing control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory having a dummy bitline for timing control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4177856