Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Patent
1994-11-16
1996-02-20
Westin, Edward P.
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
326 96, 365194, 36523006, 36523002, G11C 800, H03K 1920
Patent
active
054932416
ABSTRACT:
A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation. The circuitry includes a delay circuit for delaying the select signal, a select circuit for selecting one of the select signal and the delayed select signal to be applied to the memory array, and a resettable delay circuit for delaying a memory operation control signal for a second predetermined delay time to select one of the select signal and the delayed select signal.
REFERENCES:
patent: 4644189 (1987-02-01), Gabillard
patent: 4737670 (1988-04-01), Chan
patent: 4803665 (1989-02-01), Kasa
patent: 4807191 (1989-02-01), Flannagan
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5062082 (1991-10-01), Choi
patent: 5083294 (1992-01-01), Okajima
patent: 5214606 (1993-05-01), Hashimoto
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5267205 (1993-11-01), Hamada
patent: 5357479 (1994-10-01), Matsui
patent: 5391941 (1995-02-01), Landry
B. F. Fitzgerald et al., "Memory System with High-Performance Word Redundancy," IBM Technical Disclosure Bulletin, vol. 19, No. 5, pp. 1638-1639 (Oct. 1976).
Landry Gregory J.
Phelan Cathal G.
Cypress Semiconductor, Inc.
Roseen Richard
Westin Edward P.
LandOfFree
Memory having a decoder with improved address hold time does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory having a decoder with improved address hold time, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory having a decoder with improved address hold time will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1358405