Memory fault correction system and method

Details Memory fault correction system and method Memory fault correction system and method

1996-12-16

2000-06-13

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714768, 714764, G11C 2900

Patent

active

060761822

ABSTRACT:
A memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner. The system divides each data word into a plurality of sub-words and creates a separate error correction code for each of the sub-words. Each of the error correction codes includes a plurality of check bits with check bit values based on the data bit values of the corresponding sub-word of the data word. The computer system includes a plurality of error correction modules each performing error correction on a separate sub-word of the data word. A memory controller rearranges the data bits of the data word when forming the sub-words such that consecutive data bits are arranged in separate sub-words.

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Shanley, Tom and Don Anderson, ISA System Architecture, 3rd ed., Addison-Wesley, Reading, Mass., 1995, "Ch. 13: RAM Memory: Theory of Operation," pp. 235-272.

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