Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-03-27
2001-05-15
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S152000
Reexamination Certificate
active
06233663
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a memory control device for use in a data processing system, and in particular to a memory exclusive control device and method therefor in a data multiprocessor system for loading an initialization program and the like.
2. Description of the Prior Art
In a conventional data processing system for use in such as a data recording/reproducing system and the like using a data recording medium, there are widely used various kinds of recording medium in a data recording/reproducing player, for example, a compact disk (CD), mini disk (MD), digital video disk (DVD), PD, MO and the like. In operating a disk player, when e.g. an optical disk is rotated during a recording/reproducing operation, there have been employed various control systems, for example, a spindle motor servo-control system in the disk player for servo-controlling a spindle motor, a focus/tracking servo-control system for obtaining focus and tracking conditions of a light beam spot when using an optical disk, and error correction and data compression control systems and the like.
In order to effect such various control systems, a memory exclusive control device is employed in a data multiprocessor system for loading an initialization program.
The following describes a conventional memory exclusive control device serving as an initializing program loading device for use in a data processing system of a multiprocessor type.
FIG. 8
shows a conventional construction of a memory exclusive control device as an initializing program loading device of a multiprocessor system in a data recording/reproducing system, where the data processing system includes a first processor
815
for data processing of demodulation, error correction and the like control, a second processor
816
for focus/tracking and disk-rotation servo-controls and further includes a common memory device
805
which are interconnected via data bus lines.
The first processor
815
includes a first microprocessor
801
(referred to as “CPU-
1
” hereinafter), a first memory device
802
of RAM, a third memory device
803
of ROM which is different in type from the first memory device, a bus control unit
804
, an interface
807
and a direct memory access (referred to as “DMA” hereinafter), where the CPU-
1
is accessible to the common memory device
805
and to the first memory device
802
. The CPU-
1
is also accessible to the third memory device
803
having a specified program previously loaded thereon. The DMA
910
is interconnected with a hostcomputer.
The second processor
816
includes a second microprocessor
806
(referred to as “CPU-
2
” hereinafter) and a second memory device
808
of ROM, where the CPU-
2
is accessible to the common memory device
805
and to the second memory device
808
. The CPU-
2
is connected to a medium detecting portion
817
which is comprised of a servo microcomputer compatible to various kinds of disks or the like medium so that the CPU-
2
detects a type of a recording medium of e.g. a disk loaded to the medium detecting portion
817
.
The bus control unit
804
provided in the first processor
815
controls the bus lines for data transfer by a time sharing method between the common memory device
805
and the CPU-
1
and between the common memory device
805
and the CPU-
2
. The interface
807
provided in the first processor B
15
mutually controls the accesses of the CPU-
1
and CPU-
2
.
The second memory device
808
provided in the second processor
816
includes a first program transfer processing unit
809
(referred to as “1st PTC” hereinafter), a transfer completion setting unit
811
(referred to as “TCS” hereinafter), a second program transfer processing unit
812
(referred to as “2nd PTC” hereinafter), and a processing program storage portion
814
(referred to as “PPS” hereinafter). The 1st PTC
809
stores 1st transfer program for transferring the programs on the second memory device
808
to the common memory device
805
. When the
1
st transfer program is executed and completed, in other words, when the transfer of the programs on the second memory device
808
to the common memory device
805
is completed, the TCS
811
establishes a transfer completion indicative value on a transfer completion variable
810
(referred to as “TCV” hereinafter). The TCV
810
indicates whether or not the data transfer from the second memory device to the common memory device is completed. The 2nd PTC
812
stores a 2nd transfer program for transferring a program on the common memory device
805
to the first memory device
802
. The PPS
814
stores processing programs p
1
, p
2
, . . . for the CPU-
1
, which the programs p
1
, p
2
, . . . correspond to the types of the recording medium to be loaded, respectively.
Similarly, the common memory device
805
is also provided with a 2nd PTC
812
′, PPS
814
′ and TCV
810
′, which are corresponding to the 2nd PTC
812
, PPS
814
and TCV
810
provided in the second memory device
808
, respectively.
The third memory device
803
is provided with a transfer completion monitor processing unit
813
(referred to as “TCM” hereinafter) having a monitor processing program for monitoring whether or not the transfer of the programs from the second memory device to the common memory device is completed, with reference to the TCV
810
by a time sharing method. When the transfer completion indicative value of e.g. “1” is established in the TCV
810
by the TCS
811
, the TCM
813
detects that the program transfer onto the common memory device is completed. Then, the execution of the 2nd transfer program, which has been transferred to the 2nd PTC
812
′ on the common memory device
805
, is started, and then the program on the common memory device is transferred to the first memory device
802
. Thus, the processing program for the CPU-
1
now stored in the PPS
814
′ on the common memory device
805
is transferred to a PPS
814
″ on the first memory device
802
and then the processing program for the CPU-
1
is started to be executed on the first memory device
802
.
FIG. 9
shows an interconnection in detail between the bus control unit
804
and the CPU-
1
, CPU-
2
and various memories in the conventional construction.
In this construction shown in
FIG. 9
, when the CPU-
1
801
accesses to the common memory device
805
of DRAM, the CPU-
1
transmits a bus request signal to an adjustment unit
900
via a signal line BR
1
. In response thereto, the adjustment unit
900
transmits a bus release signal to the CPU-
1
via a signal line BG
1
. Upon transmission of the bus release signal, the address buses
901
,
905
and data buses
902
,
906
are opened to allow the CPU-
1
to transfer the data to the DRAM
805
, that is, allowing read/write of the data. Thus, the CPU-
1
accesses to the DRAM
805
via the bus control unit
804
to thereby execute the programs on the DRAM
805
by fetching the programs.
When the CPU-
2
accesses to the DRAM
805
for transferring the processing programs from the second memory device
808
, the CPU-
2
transmits a bus request signal to the adjustment unit
900
via a signal line BR
2
. In response thereto, the adjustment unit
900
transmits a bus release signal to the CPU-
2
via a signal line BG
2
. Thus, the CPU-
2
transfers the data from the second memory device
908
to the DRAM
805
via the bus control unit
804
.
Similarly, DMA transmits a DMA request signal to the adjustment unit
900
via a signal line BR
3
. In response thereto, the adjustment unit
900
transmits a bus release signal to the DMA via a signal line BG
3
. Thus, the DMA transfers the data to the DRAM
805
via the bus control unit
804
.
With reference to whether or not any of the bus request signals is present on the signal lines BR
1
, BR
2
and BR
3
, the corresponding bus release signal is transmitted to any of the CPU-
1
, CPU-
2
or DMA by switching the address and data buses by a method of time sharing.
When the bus request sig
Iwamura Yoshiyuki
Kakiage Toru
Maeda Toshinori
Yamamoto Kazushi
Ellis Kevin L.
Greenblum & Bernstein P.L.C.
Matsushita Electric - Industrial Co., Ltd.
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