Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-03-15
2005-03-15
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S133000
Reexamination Certificate
active
06868505
ABSTRACT:
Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).
REFERENCES:
patent: 4751636 (1988-06-01), Sibley
patent: 5542042 (1996-07-01), Manson
patent: 5636153 (1997-06-01), Ikegaya et al.
patent: 6347368 (2002-02-01), Harthcock
Gorski Joseph P.
Grider Stephen N.
Jones Andrew D.
Little Ann
Ma Edward Tang Kwai
Dallas Semiconductor Corporation
Iqbal Nadeem
Jenkens & Gilchrist
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