Memory error ranking

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

07493534

ABSTRACT:
An example memory error ranking system is provided. The system may include an error detector logic that detects memory errors and a ranking logic that ranks the quality of a memory location based on memory errors detected by the error detector logic.

REFERENCES:
patent: 4584681 (1986-04-01), Singh et al.
patent: 4628509 (1986-12-01), Kawaguchi
patent: 5287500 (1994-02-01), Stoppani, Jr.
patent: 5500940 (1996-03-01), Skeie
patent: 5550838 (1996-08-01), Okajima
patent: 5790886 (1998-08-01), Allen
patent: 5867642 (1999-02-01), Vivio et al.
patent: 5907854 (1999-05-01), Kerns
patent: 6096093 (2000-08-01), Caywood et al.
patent: 6130442 (2000-10-01), Di Zenzo et al.
patent: 6212647 (2001-04-01), Sims et al.
patent: 6265232 (2001-07-01), Simmons
patent: 6330621 (2001-12-01), Bakke et al.
patent: 6360340 (2002-03-01), Brown et al.
patent: 6441897 (2002-08-01), Zeimantz
patent: 6446224 (2002-09-01), Chang et al.
patent: 6553533 (2003-04-01), Demura et al.
patent: 6622270 (2003-09-01), Beffa
patent: 6813740 (2004-11-01), Lejeune
patent: 6829554 (2004-12-01), Dueregger et al.
patent: 6931509 (2005-08-01), Lloyd-Jones
patent: 6993678 (2006-01-01), Cheok et al.
patent: 7168010 (2007-01-01), Yadavalli et al.
patent: 2001/0020254 (2001-09-01), Blumenau et al.
patent: 2001/0036306 (2001-11-01), Wienecke
patent: 2001/0052102 (2001-12-01), Roohparvar
patent: 2002/0066056 (2002-05-01), Suzuki et al.
patent: 2002/0087913 (2002-07-01), Harper et al.
patent: 2002/0099996 (2002-07-01), Demura et al.
patent: 2002/0116651 (2002-08-01), Beckert et al.
patent: 2003/0023811 (2003-01-01), Kim et al.
patent: 2003/0088737 (2003-05-01), Burton
patent: 2004/0030957 (2004-02-01), Yadavalli et al.
patent: 2004/0225946 (2004-11-01), Hashimoto et al.
patent: 2004/0243692 (2004-12-01), Arnold et al.
patent: 2005/0033935 (2005-02-01), Manbert et al.
patent: 2005/0097406 (2005-05-01), Brebisson
patent: 283564 (1988-09-01), None
“Circuit complexity reduction for symbolic analysis of analog integrated circuits” by Daems et al. This paper appears in: Proceedings of 36th Design Automation Conference, Publication Date: 1999 On pp. 958-963 ISBN: 1-58113-092-9 INSPEC Accession No. 6504326.
U.S. Patent Office; Office Action for U.S. Appl. No. 10/827,946; dated Feb. 19, 2008.
U.S. Patent Office; Office Action for U.S. Appl. No. 10/827,946; dated Jun. 18, 2007.
U.S. Patent Office; Office Action for U.S. Appl. No. 10/827,946; dated Dec. 18, 2006.
U.S. Patent Office; Office Action for U.S. Appl. No. 10/827,946; dated May 2, 2006.
http://en.wikipedia.org/wiki/Interleaving.

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