Memory error containment in network cache environment via restri

Details Memory error containment in network cache environment via restri Memory error containment in network cache environment via restri

1997-09-22

2000-06-27

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711146, 711121, 711152, G06F 1214

Patent

active

06081876&

ABSTRACT:
A computer memory management system that allocates each node's network cache into protected and unprotected regions. Nodes are previously configured into error containment cluster of nodes (ECCNs). Unprotected network caches may encache data accessed from any node's unprotected memory. Protected network caches may encache data accessed from nodes that are within the same ECCN, but only from a node's protected main memory. Memory address allocation techniques known in the art enable the system to know whether a processor's request for data will be found in protected or unprotected memory. Under the present invention, a node is able to first refer to network cache (protected or unprotected, as appropriate) in locating the data. If the data is not in cache, then the system refers to main memory. The present invention thus enables superior memory access advantages of cache memory techniques. At the same time, in the event of a memory error, the present invention's protected/unprotected configuration contains the corruption caused by the error. Exemplary processing logic is also disclosed enabling the present invention in a preferred embodiment.

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patent: 5802577 (1998-09-01), Bhat et al.
patent: 5845071 (1998-12-01), Patrick et al.

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