Memory elements with increased write margin and soft error...

Details Memory elements with increased write margin and soft error... Memory elements with increased write margin and soft error...

2011-04-05

2011-04-05

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S063000, C365S072000

Reexamination Certificate

active

07920410

ABSTRACT:
Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

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