Memory element with multibit storage

Static information storage and retrieval – Systems using particular element – Superconductive

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257 31, 257 36, 505832, G11C 1144

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056108575

ABSTRACT:
A memory element for multiple bit storage uses a plurality of Josephson junction devices coupled in parallel between a ground plane and a superconductive line. A gate current is directly coupled to the superconductive line at a midpoint, and a control current is magnetically coupled to the superconductive line along its length. The current trajectory of the gate and control currents from an initial value to a quiescent point in the threshold curve traces determines the states of the modes. All the modes have a stable operating point at the quiescent point. The control current in the absence of the gate current is used to maintain the memory element at the quiescent point, and the gate current is used to momentarily transition none, one or more of the Josephson junction devices to a voltage state to determine the states of the modes at the quiescent point via appropriate Josephson sensors.

REFERENCES:
patent: 3978351 (1976-08-01), Zappe
patent: 4509146 (1985-04-01), Wang
patent: 5260264 (1993-11-01), Kurosawa
Jutzi, I.B.M. Technical Disclosure Bulletine, vol. 17, No. 3, Aug. 1974.
"Experimental Investigation of the Threshold Curves of a Four-Junction SQUID" by V. Nandakumar & Y. K. Kwong, Physica B 194-196 (1994) 111-112.
"DC Analysis of Parallel Arrays of Two and Three Josephson Junctions" by Won-Tien Tsang and T. Van Duzer, Journal of Applied Physics, vol. 46, No. 10, Oct. 1975.
"Memory-Cell Design in Josephson Technology" by Hans H. Zappe, IEEE Transactions on Electron Devices, vol. ED-27, No. 10, Oct. 1980.
"Single Flux-Quantum Josephson Memory Cell Using a New Threshold Characteristic" by Itaru Kurosawa, Akihiko Yagi, Hiroshi Nakagawa and Hisao Hayakawa.
"A 4K Josephson Memory" by H. Suzuki, N. Fujimaki, H. Tamura, T. Imamura, and S. Hasuo, IEEE Transactions on Magnetics, vol. 25, No. 2, Mar. 1989.

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