Memory element exchange control circuit capable of automatically

Details Memory element exchange control circuit capable of automatically Memory element exchange control circuit capable of automatically

1988-05-16

1990-08-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365200, 365218, G11C 700

Patent

active

049473786

ABSTRACT:
A redundant address memory circuit is used in a memory element exchange circuit associated to a memory matrix composed of FAMOS memory cells and provided with a redundant memory array composed of FAMOS memory cells. The redundant address memory circuit comprises a FAMOS memory cell for storing a defective address, and an output circuit connected to the defective address storing FAMOS memory cell for generating an output signal corresponding to the content of the defective address storing FAMOS memory cell. In addition, there is provided a circuit connected to the defective address storing FAMOS memory cell and to the output circuit for receiving the content of the defective address storing FAMOS memory cell through the output circuit so as to write the content of the defective address storing FAMOS memory cell into the defective address storing FAMOS memory cell when a new data is written to the memory matrix.

REFERENCES:
patent: 4218764 (1980-08-01), Furuta et al.
patent: 4292676 (1981-09-01), Henig
patent: 4360903 (1982-11-01), Plachno et al.
patent: 4519050 (1985-05-01), Folmsbee
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4656609 (1987-04-01), Higuchi et al.
patent: 4745582 (1988-05-01), Fukushi et al.

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