Memory efficient streamlined transmitter with a multiple...

Details Memory efficient streamlined transmitter with a multiple... Memory efficient streamlined transmitter with a multiple...

2005-03-11

2008-03-04

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07340669

ABSTRACT:
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal in response to a first intermediate signal and a second intermediate signal. The second intermediate signal comprises a series of bit pairs. The second circuit comprises a first and a second encoder and may be configured to generate the second intermediate signal in response to a third intermediate signal. The third circuit may be configured to generate the first intermediate signal and the third intermediate signal in response to a first address signal and a second address signal. The third circuit comprises a first multiplexer and a second multiplexer.

REFERENCES:
patent: 6119264 (2000-09-01), Berrou et al.
patent: 6304991 (2001-10-01), Rowitch et al.
patent: 6553516 (2003-04-01), Suda et al.
patent: 6571366 (2003-05-01), Doetsch et al.
patent: 6637000 (2003-10-01), Rowitch et al.
patent: 6954885 (2005-10-01), Hurt et al.
patent: 2005/0160347 (2005-07-01), Kim et al.

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