Memory driving method

Details Memory driving method Memory driving method

1979-10-04

1981-12-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365174, G11C 1140, G11C 1300

Patent

active

043085962

ABSTRACT:
In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

REFERENCES:
patent: 3875567 (1975-04-01), Yamazaki

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