Memory disambiguation for large instruction windows

Details Memory disambiguation for large instruction windows Memory disambiguation for large instruction windows

2003-05-15

2008-08-26

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C712S216000

Reexamination Certificate

active

07418552

ABSTRACT:
A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction window of a processor. Some store queue entries include resolved store addresses, and some do not. The store forwarding buffer is a set-associative buffer that has entries allocated for store instructions as store addresses are resolved. Each entry in the store forwarding buffer is allocated into a set determined in part by a subset of the store address. When the set in the store forwarding buffer is full, an older entry in the set is discarded in favor of the newly allocated entry. A version count buffer including an array of overflow indicators is maintained to track overflow occurrences. As load addresses are resolved for load instructions in the instruction window, the set-associative store forwarding buffer can be searched to provide memory disambiguation.

REFERENCES:
patent: 5420991 (1995-05-01), Konigsfeld et al.
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5564034 (1996-10-01), Miyake
patent: 5564111 (1996-10-01), Glew et al.
patent: 5577200 (1996-11-01), Abramson et al.
patent: 5588126 (1996-12-01), Abramson et al.
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5613083 (1997-03-01), Glew et al.
patent: 5615350 (1997-03-01), Hesson et al.
patent: 5625835 (1997-04-01), Ebcioglu et al.
patent: 5664137 (1997-09-01), Abramson et al.
patent: 5666506 (1997-09-01), Hesson et al.
patent: 5694574 (1997-12-01), Abramson et al.
patent: 5694577 (1997-12-01), Kiyohara et al.
patent: 5717882 (1998-02-01), Abramson et al.
patent: 5724536 (1998-03-01), Abramson et al.
patent: 5748937 (1998-05-01), Abramson et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 5767856 (1998-06-01), Peterson et al.
patent: 5780580 (1998-07-01), Shalaby et al.
patent: 5781572 (1998-07-01), Tahara et al.
patent: 5799165 (1998-08-01), Favor et al.
patent: 5826109 (1998-10-01), Abramson et al.
patent: 5838943 (1998-11-01), Ramagopal et al.
patent: 5860154 (1999-01-01), Abramson et al.
patent: 5878245 (1999-03-01), Johnson et al.
patent: 5881262 (1999-03-01), Abramson et al.
patent: 5884061 (1999-03-01), Hesson et al.
patent: 5897666 (1999-04-01), Mallick et al.
patent: 5948100 (1999-09-01), Hsu et al.
patent: 5956753 (1999-09-01), Glew et al.
patent: 5983335 (1999-11-01), Dwyer, III
patent: 5999727 (1999-12-01), Panwar et al.
patent: 6006326 (1999-12-01), Panwar et al.
patent: 6035387 (2000-03-01), Hsu et al.
patent: 6058472 (2000-05-01), Panwar et al.
patent: 6061351 (2000-05-01), Erimli et al.
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6141747 (2000-10-01), Witt
patent: 6145054 (2000-11-01), Mehrotra et al.
patent: 6175902 (2001-01-01), Runaldue et al.
patent: 6311261 (2001-10-01), Chamdani et al.
patent: 2003/0074530 (2003-04-01), Mahalingaiah et al.
patent: WO-99/31594 (1999-06-01), None
Chrysos, George Z., et al., “Memory Dependence Prediction Using Store Sets”,Proceedings The 25th Annual International Symposium on Computer Architecture, (Jun. 27-Jul. 1, 1998),142-153.
Franklin, Manoj, et al., “ARB: A Hardware Mechanism for Dynamic Reordering of Memory References”,IEEE Transactions on Computers, vol. 45, (May 1996),552-571.
Gopal, Sridhar, et al., “Speculative Versioning Cache”,Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture, (Feb. 1-4, 1998), 195-205.

Affiliated with

Also associated with

Rating

Memory disambiguation for large instruction windows does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory disambiguation for large instruction windows, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory disambiguation for large instruction windows will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3998269