Memory devices with verifying input/output buffer circuits...

Details Memory devices with verifying input/output buffer circuits... Memory devices with verifying input/output buffer circuits...

1998-12-18

2001-07-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C305S185000, C305S185000

Reexamination Certificate

active

06259628

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to nonvolatile memories with verifying functions for programming and erasing and the method thereof.
BACKGROUND OF THE INVENTION
Flash memories have advanced performances in accessing data, than any other kind of nonvolatile memories such as electrically erasable and programmable read only memories, for a reading and writing (or programming). The merit of high speed operation in the flash memory has been regarded to be very adaptable to portable computing apparatuses, cellular phones or digital still cameras. In general, there are two kinds of the flash memory, such as the NAND-type in which memory cells are connected from a bit line in serial, and the NOR-type in which memory cells are connected to a bit line in parallel. It is well known that the NOR-type flash memory has a competitive speed for data accessing, which makes the NOR-type be more advantageous in a high frequency memory system than the NAND-type.
Typical construction of the cell (or cell transistor) of the flash memory is shown in
FIG. 1
, which can be used for the multi-bit storage. Source
3
and drain
4
, each being formed of N+ diffused region in P+ semiconductor substrate
2
, are separated each other through a channel region which is also defined in substrate
2
. Floating gate
6
is formed over the channel region through thin insulating film
7
which is under 100 Å, and insulating film
9
, such as an O—N—O (Oxide-Nitride-Oxide) film, on floating gate
6
isolates control gate
8
from floating gate
6
. Source
3
, drain
4
, control gate
8
and substrate
2
are each connected to their corresponding voltage sources Vs (drain voltage), Vd (source voltage), Vg (gate voltage) and Vb (bulk voltage), for programming, erasing and reading operations.
In programming, as well known, a selected memory cell is programmed by means of a hot electron injection between the channel region and floating gate, in which the source and substrate are held in a ground voltage, a high voltage (e.g., Vg=10 V) is applied to the control gate and a voltage to induce the hot electrons therein, 5 V through 6 V, is provided to the drain. After programmed, a threshold voltage of the selected memory cell is increased therefrom due to deposition of electrons. To read data from the programmed cell, a voltage of about 1 V is applied to the drain, a power source voltage (or about 4.5 V) is applied to the control gate, and the source is held in the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as an blocking potential even upon the gate voltage during a read-out operation, the programmed cell is considered to as an off-cell which has a threshold voltage between 6 V and 7 V.
Erasing a memory cell is accomplished by conducting F-N (Fowler-Nordheim) tunneling effect, in which the control gate is coupled to a high negative voltage of about −10 V, and the substrate (or bulk) to a positive voltage of about 5 V, in order to induce the tunneling therebetween. While this, the drain is conditioned at a high impedance state (or a floating state). A strong electric field induced by the voltage bias conditions, between the control gate and bulk region, causes the electrons to be moved into the source. The F-N tunneling normally occurs when the electric field of 6~7 MV/cm is developed between the floating gate and bulk region which are separated through the thin insulating film under 100 Å. The erased cell has a lower threshold voltage than before, and thereby sensed as an on-cell which has a threshold voltage between 1~3 V.
In an usual architecture of a memory cell array in a flash memory, the bulk region (or the substrate) combines active regions of memory cells, so that memory cells formed in the same bulk region are spontaneously erased in the same time. Therefore, units of erasing (hereinafter referred to as “sector”, for instance, one sector of 64 K) is determined in accordance with the number of separating the bulk regions. Table 1 shows levels of the voltages used in programming, erasing and reading.
TABLE 1
operation mode
Vg
Vd
Vs
Vb
programming
10V
5~6V
0V
0V
erasing
−10V
floating
floating
5V
reading
4.5V
1V
0V
0V
After programming and erasing with the bias conditions shown in Table 1, there is a need of checking the result of the operations. Referring to
FIG. 2
, threshold voltages of memory cells which experienced the programming are positioned at about 6 through 7 V and erased threshold voltages are adjusted to be 1 V through 3 V. In an erase operation, the first step is to make the highest one of the erased threshold voltages not be over than 3 V (re-erasing for under-erased memory cells), and the second is to forcibly make over-erased threshold voltages under 1 V be shifted up to the 1 V (i.e., erase repairing for over-erased memory cells). Meanwhile, under-programmed threshold voltages under 6 V shall be forced to be shifted up to the 6 V (re-programming for under-programmed memory cells).
Whether or not a further erasing or programming needs is determined by a verifying circuit which detects a status (e.g., on-cell or off-cell) of a selected memory cell. The repairing operations of erasing and programming are each accomplished by their respective verifying processes with respective verifying circuits. Separate circuits for verifying of the programming and erasing cause the lay-out size to be increased thereof.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problems. And, it is an object of the invention to provide a nonvolatile semiconductor memory device having a single circuit for performing verifying operations for programming and erasing.
In order to accomplish those objects, the memory of the invention includes a memory cell array having the memory cells arranged in a matrix, a sense amplifier for detecting a state of the memory cell, an input/output buffer for receiving an output of the sense amplifier and for generating an output responding to the output of the sense amplifier, a verifying circuit for generating an output responding to the output of the input/output buffer, and a control logic block for receiving signals relevant to verifying operations after programming and erasing and for generating signals controlling the input/output buffer and verifying circuit. The verifying operations for programmed and erased cells are conductive through the sense amplifier, the input/output buffer and verifying circuit, in common.


REFERENCES:
patent: 5784317 (1998-07-01), Ha
patent: 5886927 (1999-03-01), Takeuchi

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