Memory devices with reduced power consumption refresh cycles

Details Memory devices with reduced power consumption refresh cycles Memory devices with reduced power consumption refresh cycles

2001-03-15

2003-05-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S185200, C365S185250, C365S149000, C365S230090

Reexamination Certificate

active

06567332

ABSTRACT:

FIELD OF THE INVENTION
The technical field relates generally to memory devices, and, more particularly, to memory devices having reduced power consumption refresh cycles.
BACKGROUND
Memory cells are commonly formed in integrated circuits by energy storage devices, such as capacitors. A capacitor is composed of two layers of a material that is electrically conductive (hereinafter, electrodes) brought near to one another and separated by a material that is electrically nonconductive. The capacitor is connected to an energy source (e.g. battery) with a certain voltage level (hereinafter, energy level). Charge flows from the energy source to the capacitor until the capacitor exhibits the energy level of the energy source. Then, the capacitor is disconnected from the energy source. The capacitor will exhibit the energy level of the energy source until the charges stored in the capacitor are removed either by design or unintentionally.
This ability of the capacitor to “remember” an energy level is valuable to the operation of semiconductor integrated circuits. Often, the operation of such circuits may require that data be stored and retrieved as desired. Because of its ability to remember, the capacitor is a major component of a semiconductor memory cell. One memory cell typically stores one bit of data. A system of memory cells is a semiconductor memory array where information can be randomly stored and retrieved from each memory cell. Such a system is also known as a random-access memory.
One type of random-access memory is dynamic random-access memory (DRAM). The charges stored in DRAM tend to unintentionally leak away over a short time. It is thus necessary to periodically refresh the charges stored in the DRAM. Even with the refresh burden, DRAM is a popular type of memory because it can occupy a very small space on a semiconductor surface. This is desirable because of the need to maximize storage capacity, i.e. the number of stored bits, on the limited surface area of an integrated circuit.
Examples of some refresh schemes are disclosed in U.S. Pat. No. 6,097,658 issued to Satoh et al.; U.S. Pat. No. 6,094,705 issued to Song; and U.S. Pat. No. 4,631,701 issued to Kappeler et al.; all incorporated herein by reference.
Many modem electronic devices are portable devices which use a battery as its energy source. As more and more portable electronic devices are developed and find commercial acceptance, it is desirable to conserve energy. Conservation of energy is driven by the need to use smaller and lighter power supplies so the electronic devices incorporating the power supply are themselves smaller and lighter. Moreover, there is a need to conserve energy so that the energy source lasts longer and the electronic device can operate longer between energy source charges or replacement. Accordingly, power consumption in memory devices used in electronic devices is becoming increasingly important.
SUMMARY
The above-mentioned problems with memory devices as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification including the drawings attached hereto. Systems, devices, structures, and methods are described which provide benefits over conventional memory devices.
An illustrative embodiment includes a method for refreshing memory cells in a memory device, wherein the refresh operation uses less energy than conventional refresh operations.
Another illustrative embodiment includes a method of conserving energy while refreshing memory cells in a memory device. One embodiment of the invention includes holding the isolation signal in a non-energized state while refreshing memory cells in an adjacent section of the memory device. The isolation signal is held in the non-energized state under a certain conditions, including but not limited to, completion of the refresh cycle, receipt of a memory address in the memory section, and receipt of a redundancy signal.
Another illustrative embodiment includes a method of reducing energy consumption during a refresh operation in a memory device. The method includes shifting an LEQ signal from an energized state to a non-energized state. The method further includes shifting an isolation signal from an energized state to a non-energized state The method further includes sequentially energizing wordlines in the memory device to refresh the memory cells connected to the energized wordline, and holding the isolation signal in a non-energized state during energizing at least two wordlines.
Another illustrative embodiment includes a memory array, which must be refreshed to preserve the integrity of the data stored therein. The memory array includes at least one memory section having a plurality of wordlines each connected to at least one memory cell. The memory cells are further connected to digit lines which are connected to a sense amplifier through isolation gates. An isolation gate control circuit holds the isolation gate off during a refresh cycle of the memory section until an end event occurs. A nend event is an event in the memory array that indicates the refresh operation is to end. In various embodiments, the end event includes, but is not limited to, at least one of completion of a self refresh cycle, addressing a memory cell in the memory section for a read or write operation, a redundancy operation, or issuance of an end refresh signal by a control circuit.
Another illustrative embodiment includes a controller for a refresh operation in a memory device. The controller holds the isolation signal at a non-energized state until an end refresh event occurs.
Other illustrative embodiments include a DRAM, a circuit module, a memory module, an electronic system, a memory system, or a computer system, which include the memory refresh structure according to the present invention or performs a memory refresh according to method of the present invention.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims and their equivalents.


REFERENCES:
patent: 4631701 (1986-12-01), Kappeler et al.
patent: 5229970 (1993-07-01), Lee et al.
patent: 5262998 (1993-11-01), Mnich et al.
patent: 5276843 (1994-01-01), Tillinghast et al.
patent: 5278796 (1994-01-01), Tillinghast et al.
patent: 5323350 (1994-06-01), McLaury
patent: 5335201 (1994-08-01), Walther et al.
patent: 5392251 (1995-02-01), Manning
patent: 5539703 (1996-07-01), Manning
patent: 5598376 (1997-01-01), Merritt et al.
patent: 5684751 (1997-11-01), Manning
patent: 5717654 (1998-02-01), Manning
patent: 5835433 (1998-11-01), Casper
patent: 5903507 (1999-05-01), Arimoto
patent: 5959924 (1999-09-01), Son et al.
patent: 5999471 (1999-12-01), Choi
patent: 6094705 (2000-07-01), Song
patent: 6097658 (2000-08-01), Satoh et al.
patent: 6208577 (2001-03-01), Mullarkey
patent: 6304494 (2001-10-01), Arimoto

Affiliated with

Also associated with

Rating

Memory devices with reduced power consumption refresh cycles does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory devices with reduced power consumption refresh cycles, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory devices with reduced power consumption refresh cycles will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3003894