Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2011-08-23
2011-08-23
Patel, Kaushikkumar (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000
Reexamination Certificate
active
08006057
ABSTRACT:
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.
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Lerner David Littenberg Krumholz & Mentlik LLP
Patel Kaushikkumar
Round Rock Research, LLC
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