Memory devices including global row decoders and operating...

Details Memory devices including global row decoders and operating... Memory devices including global row decoders and operating...

2006-04-25

2006-04-25

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S185110, C365S185130

Reexamination Certificate

active

07035162

ABSTRACT:
A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

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French Search Report for French patent Appl. No. 04 7707 mailed on Oct. 12, 2005.
Notice to Submit Reponse, Korean Appl. No. 10-2003-0047541, dated Jul. 28, 2005.

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