Memory devices and memory reading methods

Details Memory devices and memory reading methods Memory devices and memory reading methods

2000-03-07

2001-08-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S207000, C365S210130, C327S077000, C327S053000, C327S055000

Reexamination Certificate

active

06282129

ABSTRACT:

The present invention relates to comparators, memory devices, comparison methods and memory reading methods.
BACKGROUND OF THE INVENTION
A conventional track and latch comparator is shown in FIG.
1
. The signals to be compared are received in the INPUT− and INPUT+ nodes of the depicted comparator. The strobe input controls tracking and latching for evaluation of the input signals. Following the latching, the comparison result is available at the OUT− and OUT+ nodes for observation.
Another conventional track and latch comparator configuration is shown in FIG.
2
. The depicted track and latch comparator of
FIG. 2
includes NMOS devices M
11
and M
22
provided in parallel with devices M
1
, M
2
, respectively. Devices M
11
, M
22
are controlled by the respective INPUT− and INPUT+ signals which are to be compared. The strobe node again controls the tracking and latching of the depicted track and latch comparator configuration. The result of the comparison is available at the OUT+ and OUT− terminals.
The track and latch comparator configurations illustrated in FIG.
1
and
FIG. 2
provide adequate operation in balanced environments. More specifically, the depicted configurations of FIG.
1
and
FIG. 2
can be utilized where input impedances of the comparator (input and reference) match and where the outputs have minimum loading. Such applications are typically not present in conventional memory environments where numerous comparators share a common reference signal.
Track and latch comparators have been utilized in such memory environments to provide comparison of a read value from a memory storage device with a reference voltage. Such is utilized to determine whether the stored information corresponds to a logical high or a logical low value. Memory devices typically consist of a plurality of rows and a plurality of columns forming an array of memory storage locations. Data is written to the memory storage device during programming of the memory device. Individual rows usually have one associated comparator. Further, one reference voltage is provided for a whole memory device array and associated comparators in typical configurations.
Accordingly, the input impedances to the comparators are unbalanced inasmuch as one reference is used for individual comparators. Kickback noise or voltages fed into the reference device and data device (memory storage location) are different. The kickback effect on the reference device is cumulative corresponding to the number of comparators. For example, if thirty-two comparators are utilized in association with the memory array, a kickback effect on the reference source is thirty-two times worse than the kickback effect experienced by one of the data devices. Kickback noise can adversely impact the sensitivity of the associated comparator resulting in read error when small differential voltages are being analyzed.
In addition, clocks may be utilized in track and latch comparator configurations for reading data stored within the memory device. Clocks are typically utilized in such track and latch configurations to time the tracking and evaluation or comparison of the inputs. Kickback noise has been observed to be most severe during clock switching to the point of affecting the resolution of the comparator device.
Further, during evaluation or latching, additional sources of kickback noise or feed-through are output drivers of the comparator device. More specifically, during switching of the output drivers of the comparator, kickback noise couples with the comparator latching circuitry which couples back with the inputs to the comparator.
Points of current injection into a comparator stage of a conventional track and latch comparator are additional sources of kickback noise. During the evaluation of input signals, current redistribution on the current injection nodes creates a large voltage disturbance which feeds through directly to the comparator inputs. One conventional solution has been to reduce the injection current. Such may be implemented by reducing the width of converter MOS devices. However, this has been observed to lead to a severe mismatching problem on the inputs of the comparator.
Therefore, a need exists to provide improved comparator configurations and methods of comparing two input signals.


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