Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2000-03-31
2003-05-06
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S005000, C711S170000, C711S171000, C711S172000
Reexamination Certificate
active
06560686
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory device with variable bank partition architecture, which can store data by a desired bank unit and read out the stored data in various ways by dividing a memory address space to a plurality of banks and also specified an address within each of the divided banks.
BACKGROUND OF THE INVENTION
In association with development of a high speed and multi-functional CPU or the tendency for a larger memory capacity of a recording medium, feasibility of the interactive multi-media technology enabling provision of video or audio data has been becoming increasingly higher. Further, in association with popularization of Internet communications based on consolidation of communication infrastructure, it has become possible to provide real time information through a communication line.
A quantity of digital data treated in the multi-technology as described above is substantially larger as compared to a quantity of character data in the conventional technology, so that the data compression technology such as JPEG or MPEG has been developed. When a large quantity of data as described above is to be processed with a computer, a large capacity memory, which can be accessed at a high speed, is required.
The computer once reads the data stored in a recording medium such as a CD-ROM or a magnetic disk into a main memory such as a DRAM (Dynamic Random Access Memory) which can be accessed at a high speed. The data stored in the main memory is directly processed using a CPU. Thus, to process the large quantity of data as described above, it is required that the main memory can be accessed at a high speed and also that the main memory has a large memory capacity.
To achieve the objective described above, there has been developed a technology for improving the entire data processing speed by providing a primary cache memory or a secondary cache memory which can be accessed at a higher speed between the CPU and the main memory for the purpose of improving the data reuse ratio. On the other hand, as for image data, which is a main type of data to be processed in multi-media technology, it is necessary to display the image data on a display unit, such as a CRT or a liquid crystal display unit, at a high speed, so that the image data is processed by a graphic mechanism that can operate independently from the CPU.
The graphic mechanism comprises a graphic control chip that executes a draw command issued from the CPU, and a video memory in which data to be displayed on a display unit is written. The video memory is a portion of a main memory, and the CPU writes the data to be displayed therein. Recently the SDRAM (Synchronous DRAM) or SGRAM (Synchronous Graphic RAM) is often used as the video memory.
As described above, in most computer systems, a plurality of large capacity memories are distributed on a system so that a large quantity of data, especially image data such as still pictures or moving pictures can be processed at a high speed.
In the computer systems for image data processing as described above, however, the same data is often expanded over two or more successive areas. Also, when the data expanded over a plurality of areas is stored in a video memory, it is necessary to specify an address for each pixel that forms the screen of the display unit.
Especially when resolution of an image to be displayed is lower as compared to that of a display unit, it is necessary to store data corresponding to one dot in the image data over a plurality of successive storage areas on a video memory. The same necessity occurs also when image data containing scarce image information is repeatedly enlarged for display. For instance, when data for one pixel in image data is reproduced on a display unit with high resolution, the data for one pixel is displayed as a rectangle consisting of 4×4=16 dots on the display unit.
Further, a memory used as a main memory for a CPU has the same configuration as that used as a video memory, and is not specifically differentiated when shipped as a memory chip.
Further, a large capacity memory is often used in an input/output mechanism that functions as an interface with a peripheral device, such as a display unit, or in a peripheral device itself, such as the graphic mechanism as described above. In such cases, the same problem that occurs in a video memory will occur in a data buffer incorporated, for instance, in a printer.
As described above, in the conventional type of memory, it is required to execute the processing for storing the same data specifying an address to each of different sections of an area where the data is present regardless of contents of data to be stored or resolution thereof. Especially in the multi-media technology, a plurality of window screens are displayed on a display screen, and different types of processing such as enlargement or compression are executed to the window screens respectively, so that it has been required to improve the efficiency in processing for specification of addresses.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory device with variable bank partition architecture in which, by specifying a number of divisions (bank level) to divide a memory address space to a plurality of banks and further specifying an address to each of the divided banks, it is possible to store data in batch in an area in a specified bank and also to read out the stored data in various ways.
In the memory device with variable bank partition architecture according to one aspect of the present invention, data input from data input terminal is stored in all access units in a memory address area corresponding to banks specified by bank specification address signals among those obtained by dividing the memory address area according to a number of divisions specified based on a bank level signal, and the same data can be stored in a desired memory space only with one bank specification instruction (an instruction for inputting a bank level signal and a bank specification address signal) issued from a CPU of a computer.
In the memory device with variable bank partition architecture according to another aspect of the present invention, data input from the data input terminals is stored in all access units in a memory address area corresponding to a bank specified by a bank specification address signal input from an address terminal dedicated to an operation for writing data of those obtained by dividing a memory address space based on a number of divisions specified by a bank level signal, and further data at a memory address specified by an address signal input from an address terminal dedicated to an operation for reading out data is output from data output terminals.
In the memory device with variable bank partition architecture according to still another aspect of the present invention, data input from data input terminals is stored in all access units in a memory address area corresponding to a bank specified by a bank specification address signal input from the address terminal dedicated to an operation for writing data among those obtained by dividing a memory address spaced based on a number of divisions specified by a bank level signal, and data at memory addressed sequentially and automatically specified among specified memory addresses is output in response to input of a synchronizing clock.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 5588138 (1996-12-01), Bai et al.
patent: 5625797 (1997-04-01), Ferry et al.
patent: 5644749 (1997-07-01), Obayashi
patent: 5757571 (1998-05-01), Basham et al.
patent: 5956340 (1999-09-01), Afek et al.
patent: 5969893 (1999-10-01), Basham et al.
patent: 5995415 (1999-11-01), Kuo et al.
patent: 6003036 (1999-12-01), Martin
patent: 6005803 (1999-12-01), Kuo et al.
patent: 6275894 (2001-08-01), Kuo et al.
patent: 6385672 (2002-05-01), Wang et al.
Fourie Inc.
Peikari B. James
Sughrue & Mion, PLLC
LandOfFree
Memory device with variable bank partition architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device with variable bank partition architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with variable bank partition architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3017673