Memory device with test mode for controlling of bitline...

Details Memory device with test mode for controlling of bitline... Memory device with test mode for controlling of bitline...

2005-12-27

2005-12-27

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S205000, C365S233100

Reexamination Certificate

active

06980476

ABSTRACT:
A semiconductor memory device includes a memory cell connected to a bit line and a word line; a loading unit for loading data of the memory cell on the bit line by activating the word line; an amplifying unit for amplifying the loaded data of the bit line in response to a sense amplifier enable signal; and a unit for activating the sense amplifier enable signal to have a sensing margin time at a normal mode or to have an adjusted sensing margin time at a test mode, wherein the adjusted sensing margin time is determined by a timing when a predetermined input signal is inputted at the test mode.

REFERENCES:
patent: 5596538 (1997-01-01), Joo
patent: 6038180 (2000-03-01), Hoshi
patent: 6304486 (2001-10-01), Yano
patent: 11-039899 (1999-02-01), None
patent: 11-265583 (1999-09-01), None
patent: 13-101868 (2001-04-01), None

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