Memory device with SRAM interface and DRAM cells

Details Memory device with SRAM interface and DRAM cells Memory device with SRAM interface and DRAM cells

2002-12-13

2004-07-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000

Reexamination Certificate

active

06765830

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor memory device. More particularly, it relates to a semiconductor memory device with SRAM interface and DRAM cells.
2. Description of the Related Art
FIG. 1
shows a diagram of a conventional semiconductor memory device. For example, the memory cells in the conventional memory device may be one-transistor static random access memory cells (1T SRAM cells).
As shown in
FIG. 1
, a row decoder
1
receives a row address signal RAS from external circuit, decodes and outputs a row select signal RSS to a memory unit
3
and a delay circuit
5
. The delay circuit delays the row select signal a first predetermined time as a sensing enable signal SES of sense amplifier circuit
7
. One corresponding word line of the memory unit
3
is turned on according to the row select signal.
When receiving the sensing enable signal SES from the delay circuit
5
, the sense amplifier circuit
7
senses the data stored in the corresponding memory cells connected to the turned on word line, amplifies and then latches the amplified data. Finally, a column decoder
9
receives a column address signal CAS from external circuit, decodes and outputs a column select signal CSS as an output enable signal of the sense amplifier circuit
7
. The sense amplifier circuit
7
outputs corresponding data from the latched data to an output buffer
11
when receiving the column select signal.
In one access period, the convention memory device shown in
FIG. 1
, however, not only needs to wait for a sensing enable signal from the delay circuit
5
to enable the sense amplifier circuit
7
to sense and latch data but also needs to wait for column decoder
9
to decode the column address signal CAS to enable the sense amplifier circuit
7
to output a corresponding data to the output buffer
11
.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a semiconductor memory device to minimize access time thereby improving whole access speed.
In the present invention, row decoder and column decoder decode the row address signal and the column address signal to output a row select signal and a column select signal respectively at the same time. One desired word line of a memory unit is turned on according to the row select signal, and a first delay circuit delays the column select signal a first determined time and outputs to a sense amplifier circuit. The sense amplifier circuit senses the desired word line, amplifies and outputs a desired data to a latch circuit according to the column select signal. After that, the memory device can start to access the next data. Further, the delayed column select signal is also output to a second delay circuit to delay a second predetermined time as a output enable signal, and the latch circuit outputs the latched data according to the output enable signal.


REFERENCES:
patent: 4931998 (1990-06-01), Ootani et al.
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5703830 (1997-12-01), Yasuhiro
patent: 5777945 (1998-07-01), Sim et al.
patent: 5890186 (1999-03-01), Sato et al.
patent: 5901109 (1999-05-01), Miura

Affiliated with

Also associated with

Rating

Memory device with SRAM interface and DRAM cells does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device with SRAM interface and DRAM cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with SRAM interface and DRAM cells will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3219274