Memory device with split power switch

Details Memory device with split power switch Memory device with split power switch

2011-05-31

2011-05-31

Le, Vu A (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S227000

Reexamination Certificate

active

07952910

ABSTRACT:
A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

REFERENCES:
patent: 4686391 (1987-08-01), Gudaitis
patent: 5870331 (1999-02-01), Hwang et al.
patent: 6147898 (2000-11-01), Yamada
patent: 6635936 (2003-10-01), Wuu et al.
patent: 6771095 (2004-08-01), Dunlea et al.
patent: 6781870 (2004-08-01), Kushida
patent: 6903962 (2005-06-01), Nii
patent: 7092280 (2006-08-01), Joshi
patent: 7447058 (2008-11-01), Maki et al.
patent: 7502275 (2009-03-01), Nii et al.
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2006/0268626 (2006-11-01), Hamzaoglu et al.
patent: 2007/0013428 (2007-01-01), Vadi et al.
patent: 2007/0030741 (2007-02-01), Nii et al.
patent: 2008/0094878 (2008-04-01), Joshi et al.
patent: 2007018780 (2007-02-01), None
PCT International Preliminary Report on Patentability dated Aug. 13, 2009, 7 pages.
V. Degalahal et al, “Soft Errors Issues in Low-Power Caches,” IEEE Transactions on VLSI Systems, vol. 13, No. 10, Oct. 2005, pp. 1157-1166.
V. Degalahal et al, “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proceedings of the 16th International Conference on VLSI Design, Jan. 4-8, 2003, pp. 1-7.
Y. Lih et al, “A Leakage Current Replica Keeper for Dynamic Circuits,” IEEE Journal of Solid-State Circuits, vol. 42, No. 1, Jan. 2007, pp. 48-55.
M. Yamaoka et al, “90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique,” IEEE Journal of Solid-State Circuits, vol. 41, No. 3, Mar. 2006, pp. 705-711.
K. Zhang et al, “A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 146-151.
N. Mokhoff, “Digital Designer's Plight Debated at ISSCC,” http://www.eetimes.com/showArticle.jhtml? articleID=179101341, Feb. 7, 2006, pp. 1-2.
E. Seevinck et al, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 748-754.
B. Calhoun and A. Chandrakasan, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS,” Proceedings of ESSCIRC, Sep. 2005, pp. 363-366.
International Search Report for International Application No. PCT/US2006024680, dated Jan. 12, 2006, pp. 1-3.
M. Horstmann et al, “Advanced Transistor Structures for High Performance Microprocessors,” International Conference on Integrated Circuit Design and Technology, May 17-20, 2004, pp. 65-61.
H. S. Yang et al, “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEDM Technical Digest, Dec. 13-15, 2004, pp. 1075-1077.
European Search Report for European Application No. 08728581.3-1233 dated Mar. 4, 2010, 7 pages.
U.S. Office Action for U.S. Appl. No. 11/932,643 dated Dec. 7, 2009, 8 pages.
U.S. Office Action for U.S. Appl. No. 11/932,643 dated May 6, 2010, 7 pages.
U.S. Office Action for U.S. Appl. No. 11/932,643 dated Aug. 16, 2010, 6 pages.
U.S. Office Action for U.S. Appl. No. 11/932,643 dated Dec. 16, 2010, 9 pages.

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