Memory device with sensing current-reducible memory cell array

Details Memory device with sensing current-reducible memory cell array Memory device with sensing current-reducible memory cell array

1999-06-28

2001-01-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S051000, C365S063000, C365S190000, C365S205000, C365S230030

Utility Patent

active

06169697

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device with a shared sense amplifier, and more particularly to a memory cell array arrangement capable of reducing consumption of sensing current.
FIG. 1
shows arrangement of memory cell block and sense amplifier. The memory cell block includes a plurality of memory cell arrays MCA
0
-MCA
2
and sense amplifiers
10
connected to a pair of bit lines BL and /BL are arranged between adjacent memory cell arrays MCA
0
-MCA
1
and MCA
1
-MCA
2
. In the respective memory cell arrays MCA
0
-MCA
2
, a plurality of word lines WL
0
and WLi are arranged and a plurality of memory cells (not shown) are disposed at intersections of the word lines WL
0
and WL
1
and bit lines BL and /BL. The sense amplifier
10
has a folded bit line structure having a data sensing function and a data restore function using a voltage difference between bit line pair BL and /BL which are commonly connected to the adjacent memory cell arrays MCA
0
-MCA
1
and MCA
1
-MCA
2
.
As shown in FIG.1, so as to maintain lay-out pitch of the sense amplifier
10
and to share the memory cell arrays, the shared sense amplifier scheme that the sense amplifiers are disposed in the upper and lower sides of the memory cell arrays MCA
0
-MCA
2
, is adopted in the prior memory device. That is, the sense amplifier is disposed between the adjacent memory cell arrays.
The operation of the prior sense amplifier will be described in more detail as follows. In the initial state, the bit lines BL and /BL have the bit line precharge voltage Vblp (0<Vblp<Vcc). In general, the bit line precharge Vblp is Vcc/2. If corresponding one of the word lines WL
0
-WL
1
is enabled, the potential between bit line pair BL and /BL connected to selected one of the memory cells is varied by &Dgr;v.
Then, if the sense amplifier corresponding to the selected memory cell is enabled, one line of the bit line pair BL and /BL having a relatively higher potential becomes the power voltage Vcc and another line of the bit line pair BL and /BL having a relatively lower potential is becomes the ground voltage 0V so that the data of the selected memory cell is read out and the refresh operation that makes the cell data be Vcc or 0V.
Considering a storage capacitance Cs of the memory cell and a storage capacitance Cb of the bit line BL or /BL, the storage capacitance Cs of the memory cell is comparatively larger than the storage capacitance Cb of the bit line BL or /BL. In general, Cs=100 Cb. Therefore, most of current required to the sense amplifier is consumed in driving the bit lines BL and /BL.
So as to decrease the sensing current of the sense amplifier, the method for reducing the capacitance of the bit lines BL and /BL has been studied.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce sensing current with reduction of capacitance of bit line by dividing the bit line into plural bit line segments in each of memory cell arrays.
It is an aspect of the present invention to provide a memory device, comprising: a memory cell array being divided into a plurality of cell regions; a sense-amplifying means being comprised of a plurality of a first sense amplifiers disposed in the upper side of the memory cell and a plurality of second sense amplifiers disposed in the lower side of the memory cell array; a plurality of bit line pairs, each of bit line pairs being connected to the respective sense amplifiers and being divided into a plurality of bit line segment pairs; and a connection means for connecting or disconnecting the bit line segment pairs to the sense amplifiers in accordance with a plurality of control signal pairs.
The connection means includes a plurality of means, each of means being connected between adjacent bit line segment pairs and being for connecting the bit line segment pairs to corresponding one of sense amplifiers under the control of the control signal pairs. Each means of the connection means is comprised of a pass transistor group controlled by the control signal pairs, the pass transistor group in the respective connection means including a first pass transistor pair for connecting the corresponding one of sense amplifiers to corresponding ones of the bit line segment pairs, respectively under the control of the first control signal of the respective control signal pairs; and a second pass transistor pair for connecting the corresponding one of sense amplifiers to corresponding ones of the bit line segment pairs, respectively under the control of the second signal of the respective control signal pairs.
The memory device further comprises a control circuit for receiving a plurality of cell region selection signals for selecting corresponding one of the plurality of cell regions to generate the plurality of control signal pairs to the connection means. The control circuit includes a plurality of control means, each of control means for receiving corresponding one of cell region selection signals to generate corresponding pairs of the control signal pairs to each of means of the connection means. The last control means of the plurality of control means includes a first NOR gate for receiving the corresponding one of the cell region selection signals and a ground signal to generating the first control signal of a last control signal pair of the control signal pairs; and a first inverting gate for inverting an output of the first NOR gate to generate the second control signal of the last control signal pair and another control means, each includes a second NOR gate for receiving the respective corresponding one of the cell region selection signals and the respective first control signal generated from each of next control means to generate the first control signal of the respective control signal pairs; and a second inverting gate for inverting an output of the second NOR gate to generate the second control signal of the respective control signal pairs.
In the memory device, when one of the cell regions in the memory cell array is selected by the corresponding one of the cell region selection signals, of the control signal pairs generated from the first control means through the control means corresponding to a selected cell region, the first control signals is enabled and the second control signals is disabled and of the control signal pairs generated from another control means, the first control signals is disabled and the second control signals is enabled. In case of the bit line pairs connected to the plurality of first sense amplifiers, the first pass transistor pairs of pass transistor groups of a first connection means to connection means corresponding to the selected cell region of the plurality of connection mean are turned on by the first control signals of enable state generated from the corresponding control means and the first pass transistor pairs of another connection means in the plurality of the connection means are turned off by the first control signals of disable state generated from the corresponding control means. On the other hand, in case of the bit line pairs connected to the plurality of second sense amplifiers, the second pass transistor pairs of pass transistor groups of a first connection means to connection means corresponding to the selected cell region in the plurality of connection mean are turned off by the second control signals of disable state generated from the corresponding control means and the second pass transistor pairs of another connection means in the plurality of the connection means are turned on by the second control signals of enable state generated from the corresponding control means.
There is also provided to a memory device, comprising: a memory cell array being divided into a plurality of cell regions; a sense-amplifying means being comprised of a plurality of a first sense amplifiers disposed in the upper side of the memory cell and a plurality of second sense amplifiers disposed in the lower side of the memory cell array; a plurality of bit line pairs, each of bit line pa

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