Memory device with sense amplifier and self-timed latch

Details Memory device with sense amplifier and self-timed latch Memory device with sense amplifier and self-timed latch

2005-03-01

2005-03-01

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S205000

Reexamination Certificate

active

06862208

ABSTRACT:
A memory device (201) includes a plurality of memory cells (203), bit lines, word lines, a sense amplifier (314), and a self-timed latch (215). The sense amplifier (314), responsive to a sense enable signal, is for sensing and amplifying a voltage on the bit lines corresponding to a stored logic state of a selected one of the plurality of memory cells. An isolation circuit (306, 308) is coupled between the bit lines (205and207) and the sense amplifier (314). The isolation circuit (306, 308) is for decoupling the selected one of the plurality of memory cells from the sense amplifier (314) at about the same time that the sense enable signal is asserted. A self-timed latch (215) is coupled to the sense amplifier (314). The self-timed latch (215) does not receive a clock signal and is responsive to only the amplified voltage.

REFERENCES:
patent: 5701268 (1997-12-01), Lee et al.
patent: 6101145 (2000-08-01), Nicholes
patent: 6445632 (2002-09-01), Sakamoto

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