Memory device with sense amp equilibration circuit

Details Memory device with sense amp equilibration circuit Memory device with sense amp equilibration circuit

2002-06-19

2004-01-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000, C365S205000

Reexamination Certificate

active

06678199

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of integrated memory circuits and, more particularly, to a memory device with sense amp equilibration circuit.
2. Description of the Related Art
Memory circuits, such as dynamic random access memory (DRAM) arrays, have increased in complexity and density over time. With such increased density and complexity, it is very likely that one or more shorts will occur between a word line (generally referred to as a “row” within the array) and a data line (generally referred to as a “column” within the array).
A row-to-column short typically is a point defect that shorts together a particular row line to a perpendicular data line. Such a defect generally ruins the integrity of both the row and column. Spare rows and columns are created within the DRAM array in combination with address redirection circuitry to substitute functional spare rows and columns for those that are shorted, at least to the extent that shorted rows and columns do not exceed the number of spare rows and columns. Even though this on-chip redundancy allows for the repair of a DRAM integrated circuit device, it is important to note that the shorted columns and rows are not disconnected from the array circuitry. The shorted columns and rows are merely no longer addressed by the array's address decode circuitry. Disconnection of the shorted rows and columns from the array circuitry is impractical with presently available technology due to the small pitch used to fabricate DRAM arrays. Schemes for implementing row and column redundancy in DRAM arrays are well known in the art.
The repair of row to column shorts through redirected addressing does not eliminate the presence of shorts within the array, nor does it eliminate the potential for biased voltage pull down with the attendant problems of excessive standby current, read/write operations resulting in invalid data and possible damage to cell capacitors within the array. For example, one serious problem is that of an increase in the quiescent standby current because of a defect in the circuit. In standby mode, all the row lines are actively held to ground, while the digits are ideally held to an intermediate supply voltage known as DVC2 (i.e., half of the operating voltage VCC) in anticipation of a new access. The row-to-column short therefore acts to short DVC2 to ground, giving a much higher standby current than is otherwise necessary or desired. Since such short defects cannot be eradicated entirely, large DRAM arrays have resorted to the use of “bleeder” circuits, which act to limit the amount of supply current that actively holds a digit line to DVC2.
As DRAM array sizes grow, however, row-to-column shorts become more prevalent. As such, there is a desire to reduce the standby current even further to allow the use of dice with a substantial number of row/column shorts and to keep the quiescent standby current in a more tightly controlled range. An exemplary memory device with a bleeder circuit is described in U.S. Pat. No. 6,078,538, entitled “METHOD AND APPARATUS FOR REDUCING BLEED CURRENTS WITHIN A DRAM ARRAY HAVING ROW-TO-ROW COLUMN SHORTS,” and incorporated herein by reference in its entirety.
One potential limitation regarding the use of a bleeder circuit is that in some implementations the speed of the sense amp circuitry used to sense the value stored in the memory cells may be reduced. The sense amp circuit typically has activation lines used to activate the data lines responsive to the values stored in the memory cells. To reduce standby currents, one of the activation lines may be grounded prior to a memory read cycle. The signal on the grounded activation line must then pass the entire range from ground to VCC to pull the data line to the desired state. The need for this full range swing reduces the response time of the sense amp circuitry. As operating voltages decrease, the sense amp circuit becomes slower, because of the lower NMOS gate-to-source voltage (V
GS
).
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a device including first and second data lines, a memory cell, a sense amp, equilibration circuitry, and sense amp equilibration circuitry. The memory cell is coupled to the first and second data lines. The sense amp is coupled to the data lines. The sense amp includes sensing circuitry configured to detect a voltage on the data lines corresponding to charge stored in the memory cell, a first activation line coupled between the sensing circuitry and a pullup voltage source, and a second activation line coupled between the sensing circuitry and a pulldown voltage source. The equilibration circuitry is configured to ground the first activation line and equilibrate the second activation line responsive to an assertion of an equilibrate signal. The sense amp equilibration circuitry is configured to equilibrate the first activation line responsive to an assertion of a sense amp equilibration signal prior to an activation of the second activation line.
Another aspect of the present invention is seen in a method for reading a memory cell. The method includes providing a memory cell coupled to first and second data lines. Sensing circuitry for sensing a voltage on the data lines corresponding to charge stored in the memory cell is provided. A first activation line is coupled between the sensing circuitry and a pullup voltage source. A second activation line is coupled between the sensing circuitry and a pulldown voltage source. The first activation line is grounded and the second activation line is equilibrated responsive to an assertion of an equilibrate signal. The first activation line is equilibrated responsive to an assertion of a sense amp equilibration signal prior to an activation of the second activation line.


REFERENCES:
patent: 5668765 (1997-09-01), Ang
patent: 5923603 (1999-07-01), Pinney
patent: 6078538 (2000-06-01), Ma et al.
patent: 6111803 (2000-08-01), Derner et al.
patent: 6240026 (2001-05-01), Laurent et al.

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