Memory device with self-refresh operations

Details Memory device with self-refresh operations Memory device with self-refresh operations

2011-06-14

2011-06-14

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S227000, C365S228000, C365S230060, C365S233500, C365S236000

Reexamination Certificate

active

07961541

ABSTRACT:
An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.

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