Memory device with reduced word line resistance

Details Memory device with reduced word line resistance Memory device with reduced word line resistance

2007-05-08

2007-05-08

Dinh, Son (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S063000, C365S163000

Reexamination Certificate

active

11035205

ABSTRACT:
A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

REFERENCES:
patent: 5337279 (1994-08-01), Gregory et al.
patent: 5808500 (1998-09-01), Kalpakjian
patent: 5896344 (1999-04-01), Kirsch et al.
patent: 6031784 (2000-02-01), Ong
patent: 6850432 (2005-02-01), Lu et al.
patent: 7009908 (2006-03-01), Fischer
patent: 2003/0002338 (2003-01-01), Xu et al.
patent: 2003/0133325 (2003-07-01), Silvagni et al.

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