Memory device with reduced leakage current

Details Memory device with reduced leakage current Memory device with reduced leakage current

2007-07-10

2007-07-10

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S189090

Reexamination Certificate

active

11322178

ABSTRACT:
A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.

REFERENCES:
patent: 5345216 (1994-09-01), Chopra et al.
patent: 6320795 (2001-11-01), Balamurugan et al.
patent: 7113430 (2006-09-01), Hoefler et al.
patent: 2005/0105334 (2005-05-01), Futatsuyama
patent: 2005/0195656 (2005-09-01), Chen
patent: 2005/0248976 (2005-11-01), Huang et al.
patent: 2005/0254302 (2005-11-01), Noguchi

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