Memory device with reduced cell area

Details Memory device with reduced cell area Memory device with reduced cell area

2006-03-28

2006-03-28

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S344000, C257S408000

Reexamination Certificate

active

07019356

ABSTRACT:
The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

REFERENCES:
patent: 6617637 (2003-09-01), Hsu et al.
patent: 6674119 (2004-01-01), Hashimoto et al.
patent: 2002/0190310 (2002-12-01), Boivin

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