Memory device with receives write masking information

Details Memory device with receives write masking information Memory device with receives write masking information

2002-05-17

2004-01-20

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S189020

Reexamination Certificate

active

06681288

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic memories for data storage. More particularly, the present invention relates to ways of providing a memory with write enable information.
BACKGROUND OF THE INVENTION
Digital information can be stored in various types of memories, including random access memories (“RAMs”), electrically erasable read-only memories (“EEPROMs”), flash memories, etc. Data is typically stored in a two-dimensional array in which one row of bits is accessed at a time.
A RAM is a volatile memory that can be erased and written to relatively quickly, but which loses its data when power is removed. A RAM can be either static (i.e., an “SRAM”) or dynamic (i.e., a “DRAM”). In an SRAM, once data is written to a memory cell, the data remains stored as long as power is applied to the chip, unless the same memory cell is written again. In a DRAM, the data stored in a memory cell must be periodically refreshed by reading the data and then writing it back again, or else the data in the cell disappears.
FIG. 1
shows a block diagram of a prior DRAM
10
. DRAM
10
typically is part of a computer system that includes a high speed bus
19
and a DRAM controller. DRAM
10
includes DRAM array
11
, which consists of one or more banks. For example, array
11
has Bank
0
and Bank
1
. Interface
18
contains logic for processing and routing signals entering and leaving DRAM array
11
. Signals enter and leave DRAM
10
on interface pins
6
which connect to bus
19
. The number of pins making up interface pins
6
depends upon the width of bus
19
and also upon the bus protocol used by a computer system to which the DRAM is connected.
FIG. 2
shows how interface
18
communicates with Bank
0
of array
11
of DRAM
10
. Bank
0
of array
11
can store “t” units of data. A unit of data can be a byte, and the byte is defined as being “s” bits wide, where in this case “s” is 8 bits or 9 bits (i.e., a X8 byte or a X9 byte). Address interface
60
provides column and row address signals
42
and
44
. Data interfaces
51
through
53
transfer data to and from array bank
11
into and out of DRAM
10
. Data to be read out of Bank
0
of array
11
is carried on R lines
38
, and data to be written to Bank
0
of array
11
is carried on W lines
36
. For example, data interface
51
provides for conveyance of data bits [t−
1
:
0
][
0
], these bits being the 0th bits of each of bytes
0
through t−
1
of Bank
0
of array
11
, or all the 0th bits of the bytes to be transferred. Similarly, data interface
52
carries all the 1th bits of Bank
0
of array
11
.
Write enable (“WE”) interface
56
provides a WE signal for each byte of data of Bank
0
of array
11
. Signals WE [t−
1
:
0
] are WE signals for byte
0
through byte t−
1
. The WE signals are carried on WE lines
34
. A WE signal indicates whether an associated byte is to be written or not written during a write operation.
Control interface
58
provides the following signals: column access strobe (“CAS”)
62
, row access strobe (“RAS”)
64
, and Read/Write (“W/R”) signal
66
. RAS and CAS are timing signals indicating a row or column access. W/R
66
specifies whether an operation is a write operation or a read operation
FIG. 3
shows the types of inputs to prior DRAMs. Various types of prior DRAMs have provided various separate pins for the following inputs: row address
74
, column address
76
, read and write data
78
, a write/read input signal
82
, the RAS
84
, the CAS
86
, and write enable signals
80
. Having separate pins for each of these inputs to the DRAM is relatively inefficient because the pins take up space and not all of the signals overlap in time.
For DRAMs using, different signals that are not active at the same point in time, several prior methods have been used to permit the sharing of pins, however. The sharing of pins minimizes the pin count without adversely affecting functionality.
One prior method for conserving DRAM interface pins is column/row address multiplexing.
FIG. 4
illustrates column and row address multiplexing.
FIG. 4
shows that one column and row address pin Arc[Nrc-
1
:
0
]
92
handles column and row address inputs
76
and
74
of FIG.
3
. Tis is possible because column and row address signals are not active at the same time.
Another prior method is data in/out multiplexing. Data to be read and written is multiplexed onto the same pins of a DRAM. This is also referred to as Write/Read multiplexing or W/R multiplexing.
FIG. 5
illustrates W/R multiplexing, in which data read from or written to a DRAM uses the same pins
102
for communicating with the exterior of the DRAM. Data is not read from and written to a DRAM at the same time, and thus it is possible to share data pins.
FIG. 6
illustrates another prior method of bit multiplexing, called data byte multiplexing. For data byte multiplexing, “t” data bits are transferred in serial over the same pin. For one prior art scheme, “t” equals 8. Each data bit is from a different byte. This is possible in prior DRAMs in which the internal RAM cycle rate, sometimes referred to as Column Access Strobe (“CAS”) cycle rate, is slower than the DRAM input/output (“I/O”) cycle rate.
For the example shown in
FIG. 6
, the I/O cycle rate is “t” times faster than the CAS cycle rate. Thus, if a block of data is “t” bytes, and one bit of each byte is to be transferred in a CAS cycle, then only one pin per “t” bits is needed during one CAS cycle for data transfer. For these reasons pins
202
can replace pins
102
of
FIG. 5
, and the number of data pins is reduced by a factor of “t.”
In
FIG. 7
, another prior bit multiplexing method is shown. This method is used in typical prior DRAM systems in, which row address signals and data signals are not transferred at the same time. Pins
302
transmit read and write data, but also carry row address signals
44
, thus eliminating the need for pins
74
of FIG.
3
. The column address requires dedicated column address pins
76
because column address information can be transferred at the same time data is transferred.
For the above described prior methods, dedicated WE pins are required. In prior memories in which WE signals travel a longer path to DRAM array
11
then do data signals, dedicated registers are required to hold data during the wait for WE signals. The WE signals indicate whether the data is to be written or not written to DRAM array
11
.
FIG. 8A
shows a prior art memory configuration using RDRAMs™ (“Rambus DRAMs”) of Rambus, Inc. of Mountain View, Calif.
FIG. 8B
shows how WE information is multiplexed for that Rambus memory configuration. As shown in
FIG. 8B
, eight eight-bit wide WE words comprising WE block
981
are transmitted into a RDRAM over the nine-bit wide data bus and enter the RDRAM through pins BusData [
7
] through BusData [
0
] of data pins
980
. The ninth data pin, pin BusData [
8
], is not used for transmission of the WE words. The WE words are stored in registers of the RDRAM. Each WE word is associated with a respective one of eight data blocks. Each data block is eight bytes long. Each data byte is also referred to as a data word. Each bit of each of the WE words is associated with a respective one of the eight data bytes in the respective block, which are each eight bits wide and are sent over the data bus and to the data pins of the RDRAM. Each bit of the WE word determines whether or not the associated data byte is written to the RDRAM. For example, the first WE word in WE block
981
pertains to DataBlock
0
. Bit
0
of the first WE word determines whether data byte
1000
is written. Bit
1
of the first WE word determines whether data byte
1001
is written, and so on. Similarly, each WE word pertains to a data block until the final WE word of WE block
981
determines whether data bytes in DataBlock
7
are written. For this prior art scheme, a single clock cycle has two phases, allowing two transfer operations to occur withi

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