Memory device with propagation circuitry in each sub-array...

Details Memory device with propagation circuitry in each sub-array... Memory device with propagation circuitry in each sub-array...

2011-08-16

2011-08-16

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S189140, C365S189170, C365S189050, C365S230030, C365S233190

Reexamination Certificate

active

08000156

ABSTRACT:
A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power.

REFERENCES:
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5668761 (1997-09-01), Muhich et al.
patent: 2010/0103747 (2010-04-01), Van Winkelhoff et al.

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