Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1994-03-22
1995-08-29
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Data refresh
3652257, G11C 700
Patent
active
054466954
ABSTRACT:
A programmable self-timed refresh circuit for a semiconductor memory array and methods for programming the self-refresh rate and for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.
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Douse David E.
Ellis Wayne F.
Hedberg Erik L.
International Business Machines - Corporation
Le Vu A.
Nelms David C.
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