Memory device with pipelined column address path

Details Memory device with pipelined column address path Memory device with pipelined column address path

1997-06-20

1999-12-21

Dinh, Son T.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365200, 36523003, 36523006, G11C 800

Patent

active

060058234

ABSTRACT:
In a packetized memory device, pipelined row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The column path also includes a set of bank address latches so that bank addresses can be pipelined synchronously with column addresses. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array. The bank address latches also activate a selected bank responsive to the strobe.

REFERENCES:
patent: 5305276 (1994-04-01), Uenoyama
patent: 5341341 (1994-08-01), Fukuzo
patent: 5825711 (1998-10-01), Manning
patent: 5831922 (1998-11-01), Choi
patent: 5831929 (1998-11-01), Manning
patent: 5848025 (1998-12-01), Marietta et al.
patent: 5859809 (1999-01-01), Kim
Descriptive literature entitled, "400 MHz SLDRAM, 4M .times. 16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation", pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)", Microporcessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.

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