Memory device with on-chip manufacturing and memory cell defect

Details Memory device with on-chip manufacturing and memory cell defect Memory device with on-chip manufacturing and memory cell defect

1997-04-03

1998-05-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365200, 36523006, 36518911, 365203, 371 211, G11C 700, G11C 800, G11C 2900

Patent

active

057485453

ABSTRACT:
A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line. Short circuiting between word lines and bit lines, and the maximum and minimum threshold voltages of the memory cells can also be detected in the disclosed memory device.

REFERENCES:
patent: 4914632 (1990-04-01), Fujishima et al.
patent: 5343431 (1994-08-01), Ohtsuka et al.
patent: 5351214 (1994-09-01), Rouy
patent: 5400344 (1995-03-01), Mori
patent: 5428621 (1995-06-01), Mehrotra et al.
patent: 5539694 (1996-07-01), Rouy
patent: 5606527 (1997-02-01), Kwack et al.

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