Memory device with multistage sense amplifier

Details Memory device with multistage sense amplifier Memory device with multistage sense amplifier

2007-11-06

2007-11-06

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S149000, C365S150000, C365S189020

Reexamination Certificate

active

11153829

ABSTRACT:
A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evaluated. The binary data signals can also be written back to the corresponding memory cell. Furthermore, an output unit for outputting the amplified and evaluated binary data signals and a coupling device between the memory cell array and the sense amplifier are provided. The coupling device has a preamplifier unit for preamplifying the data signals read out and a bridging unit for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.

REFERENCES:
patent: 6104655 (2000-08-01), Tanoi et al.
patent: 6781894 (2004-08-01), Taito
patent: 2001/0028588 (2001-10-01), Yamada et al.
German Office Action dated Mar. 22, 2005.

Affiliated with

Also associated with

Rating

Memory device with multistage sense amplifier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device with multistage sense amplifier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with multistage sense amplifier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3827673