Memory device with multiple read ports

Details Memory device with multiple read ports Memory device with multiple read ports

1992-06-16

1994-03-29

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523005, 36523008, 36518905, G11C 1134

Patent

active

052991580

ABSTRACT:
A memory device having a plurality of read ports which can be dumped simultaneously without affecting the data stored in the memory cells of the memory device. The read ports of the memory device of the invention include dump circuits comprising a pair of small NFETs which logically AND the values stored in the memory cell with a READ input signal and then pull low a precharged output line only when both of these signals are true. Each such read port dump circuit is electrically isolated from the others so that multiple read ports can be dumped simultaneously with affecting the data stored in the memory device. Also, by placing only a single transistor in the read port discharge path, the dump circuit may be small and have a minimal impact on write setup time in accordance with the invention.

REFERENCES:
"Port-Multiplexed Register File", IBM TDB, vol. 27, No. 5, Apr. 1985, pp. 6570-6571.
DeLano et al., "A High Speed Superscalar PA-RISK Processor" Proceedings of the Compcon Spring 1992, Digest of papers, San Francisco, Calif.; Feb. 24-28, 1992.

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