Memory device with multiple processors having parallel access to

Details Memory device with multiple processors having parallel access to Memory device with multiple processors having parallel access to

1996-07-24

1999-09-21

Swann, Tod R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 36518902, 36523002, 36523003, 711150, 395382, 395391, G06F 1316, G06F 938

Patent

active

059562749

ABSTRACT:
A random access memory chip comprising static random access storage elements, word lines and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer comprising in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing an operation function on each bit of the data in parallel to provide a result.

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patent: 5093722 (1992-03-01), Miyaguchi
patent: 5105387 (1992-04-01), Childers
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patent: 5321510 (1994-06-01), Childers
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patent: 5426610 (1995-06-01), Childers

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