Memory device with MOS transistors having bodies biased by tempe

Details Memory device with MOS transistors having bodies biased by tempe Memory device with MOS transistors having bodies biased by tempe

1995-08-15

1997-02-11

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Differential sensing

365212, 36518909, 326 31, 326 32, 326 33, 326 34, 327157, 327540, 327541, 257368, H03K 190175

Patent

active

056027907

ABSTRACT:
A memory device includes a plurality of PMOS transistors and a voltage regulator circuit. Each transistor has a gate, a source region, a drain region, and a well containing the source and drain regions. Each transistor is characterized by a threshold voltage which is dependent on temperature and on a body-source bias voltage. Each transistor is also characterized by a sub-threshold current which is dependent on the transistor's threshold voltage. The voltage regulator circuit is operatively coupled to each well to provide the body-source bias voltage to each well. The voltage regulator circuit temperature-compensates the body-source bias voltage to maintain the threshold voltage of each transistor approximately constant despite changes in temperature. The memory device thus advantageously has a relatively constant stand-by current despite temperature variations.

REFERENCES:
patent: 5063304 (1991-11-01), Iyengar
patent: 5191244 (1993-03-01), Runaldue et al.
patent: 5382843 (1995-01-01), Gucyski
patent: 5396114 (1995-03-01), Lee et al.
patent: 5488247 (1996-01-01), Sakurai
patent: 5506540 (1996-04-01), Sakurai et al.
patent: 5530394 (1996-06-01), Blosfeld et al.
Micron Semiconductor, Inc., Schematic of Circuit used in DRAMs since before Aug. 15, 1995. (single schematic, 2 pages).

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