Memory device with low resistance buried bit lines

Details Memory device with low resistance buried bit lines Memory device with low resistance buried bit lines

2002-08-15

2003-09-23

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S905000

Reexamination Certificate

active

06624460

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a memory device and a method for fabricating the same. More particularly, the present invention relates to a memory device that has a dual damascene structure with a self-aligned contact and therefore has higher reliability, and relates to a method for fabricating the memory device.
2. Description of Related Art
Memory device is a semiconductor device for storing digital data, and the size of a memory chip is usually expressed in bits. A memory device is constituted by rows and columns of memory cells, each of which stores one bit of data and has a specific address according to its location, i.e., the numbers of the row and the column where the memory cell is located. In a memory device, the memory cells in the same row/column are coupled to one conductive line.
FIG. 1
illustrates a perspective view of a memory device in the prior art.
Refer to
FIG. 1
, a method for fabricating the memory device is described below. A gate oxide layer
102
is formed on a substrate
100
, and then buried bit lines
104
are formed in the substrate
100
. Insulating oxide layers
106
are formed on the buried bit lines
104
. Word lines
108
are then formed on the substrate
100
crossing over the buried bit lines
104
and the insulating oxide layers
106
, wherein the word lines
108
are isolated from the buried bit lines
104
by the insulating oxide layers
106
.
As the areas of memory devices are reduced in accompany with higher integration of semiconductor devices, the width of buried bit lines has to be decreased. However, the miniaturization of the buried bit lines increases the resistance thereof, and the increased resistance causes overloading of the buried bit lines. The overloading problem can be solved by increasing the junction depth of the buried bit lines, but such a method results in short channel effect and junction leakage. On the other hand, the source/drain can be formed with a shallower junction and a higher dopant concentration to avoid overloading, short channel effect and junction leakage, and to lower the resistance simultaneously. However, the strategy is usually not effective in preventing overloading because of the restriction of solid state solubility. Moreover, in a conventional memory device, a bit line contact is formed on a buried bit line every 32 or 64 memory cells. However, the incorporation of the bit line contacts limits the integration of the memory device. Therefore, it is very important to decrease the number of the bit line contacts in order to increase the integration of the memory device.
SUMMARY OF INVENTION
Accordingly, this invention provides a memory device and a method for fabricating the same to lower the resistance of buried bit lines.
This invention also aims to decrease the required junction depth of buried bit lines for preventing short channel effect and punch-through leakage.
This invention further aims to decrease the number of bit line contacts in a memory device for increasing the integration of the memory device.
A memory device of this invention comprises rows and columns of memory cells. The memory device comprises a substrate, a plurality of buried bit lines, a plurality of word line structures, a dielectric layer, a plurality of conductive lines in trenches and a plurality of self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer under the word line, a capping layer on the top of the word line, and a spacer on the sidewalls of the capping layer and the word line. Each conductive line is disposed in the dielectric layer and over one buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines, that is, the conductive lines are isolated from each other by the dielectric layer. Each self-aligned contact is disposed under a conductive line and between two adjacent word line structures to electrically connect the conductive line and the corresponding buried bit line. In this invention, a conductive line and the buried bit line located under it together serve as a bit line.
A method for fabricating a memory device of this invention comprises the following steps. A buried bit line is formed in a substrate, and then a gate oxide layer is formed on the substrate. A word line having a capping layer thereon is formed on the gate oxide layer, and a spacer is formed on the sidewalls of the capping layer and the word line. A dielectric layer is formed on the substrate covering the capping layers, and then patterned to form a trench over the buried bit line exposing a portion of the capping layer. A self-aligned contact opening, which constitutes a dual damascene opening with the trench, is then formed in the dielectric layer under the trench to expose a portion of the buried bit line. In the step of forming the trench and the self-aligned contact opening, the etching rates of the capping layer and the spacer both are lower than that of the dielectric layer so that the word line is not damaged. Thereafter, a conductive material is filled into the dual damascene opening to form a dual damascene structure consisting of a conductive line in the trench and a self-aligned contact in the self-aligned contact opening. The conductive line and the buried bit line together constitute a bit line and are electrically connected via the self-aligned contact. Besides, it is also feasible to form the trench after the self-aligned contact opening is formed.
Since a bit line is constituted by a buried bit line and a conductive line in this invention, the resistance of the bit line is lower. Because of that, the buried bit line can be formed with a shallower junction to prevent short channel effect and junction leakage and improve the reliability of the memory device. Meanwhile, the voltage drop of the bit line can be reduce, so the number of bit line contacts can be decreased to increase the integration of the memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5796136 (1998-08-01), Shinkawata
patent: 6355520 (2002-03-01), Park et al.
patent: 6496402 (2002-12-01), Somasekhar et al.

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