Memory device with improved common data line bias arrangement

Details Memory device with improved common data line bias arrangement Memory device with improved common data line bias arrangement

1989-10-19

1991-09-17

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, 365190, 365177, 365208, 307530, G11C 11413

Patent

active

050501275

ABSTRACT:
A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

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Miyamoto et al., "A 28ns CMOS SRAM With Bipolar Sense Amplifiers", ISSCC Dig. of Tech. Papers, Feb. 23, 1984, pp. 224-225, 344.

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