Memory device with improved common data line bias arrangement

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

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365190, 365177, 365208, 307495, 3072967, G11C 1140, G11C 700

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active

048294799

ABSTRACT:
A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

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patent: 4430582 (1984-02-01), Bose et al.
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4604533 (1986-08-01), Miyamoto et al.
patent: 4658159 (1987-04-01), Miyamoto
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patent: 4719373 (1988-01-01), Masuda et al.
Miyamoto et al, "A 28 ns CMOS SRAM with Bipolar Sense Amplifiers", IEEE ISSCC, Feb. 23, 1984, pp. 224-225.

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